About Us

Prof. Wong joined Stanford in September, 2004 after 16 years at IBM Research, T.J. Watson Research Center, Yorktown Heights, New York.

While at IBM, he worked on CCD and CMOS image sensors, double-gate/multi-gate MOSFET, device simulations for advanced/novel MOSFET, strained silicon, wafer bonding, ultra-thin body SOI, extremely short gate FET, germanium MOSFET, carbon nanotube FET, and phase change memory. He held various positions from Research Staff Member to Manager, and Senior Manager. While he was Senior Manager, he had the responsibility of shaping and executing IBM's strategy on nanoscale science and technology as well as exploratory silicon devices and semiconductor technology.

His research interests are in nanoscale science and technology, semiconductor technology, solid state devices, and electronic imaging. He is interested in exploring new materials, novel fabrication techniques, and novel device concepts for future nanoelectronics systems. Novel devices often enable new concepts in circuit and system designs. His research also includes explorations into circuits and systems that are device-driven.

He is a Fellow of the IEEE and served on the IEEE Electron Devices Society (EDS) as elected AdCom member from 2001 - 2006. He serves on the IEDM committee from 1998 to 2007 and is the Technical Program Chair in 2006 and General Chair in 2007. He served on the ISSCC program committee from 1998 - 2004, and was the Chair of the Image Sensors, Displays, and MEMS subcommittee from 2003-2004. He was the Editor-in-Chief of the IEEE Transactions on Nanotechnology in 2005 - 2006. He is a Distinguished Lecturer of the IEEE EDS and Solid-State Circuit Society. He has taught several short courses at the IEDM, ISSCC, Symp. VLSI Technology, SOI conference, ESSDERC, and SPIE conferences. He is a member of the Emerging Research Devices Working Group of the International Technology Roadmap for Semiconductors (ITRS).

Deji Akinwande received both the B.S. and M.S. degrees in Electrical Engineering and Applied Physics from Case Western Reserve University, Cleveland, Ohio. His master's research involved the design, development and characterization of evanescent microwave probes for non-destructive imaging of materials. After graduation, he made "real" income and gained "real" experience designing and testing a variety of analog circuits from MHz to 110 GHz for network analyzer and signal generator instruments at Agilent Technologies in northern California. He subsequently worked at XtremeSpectrum/Freescale in Virginia on the modeling, design and testing of the first commercial 100 Mb/s ultra-wideband receiver chip.

He is a co-inventor of a high frequency interconnect, and received the "2005 Cheezy Award" from Prof. Tom Lee for outstanding LNA design in "EE314 RF intergrated circuits". He is a recipient of the Ford Foundation and Sloan pre-doctoral Fellowships, and the inaugural DARE fellowship from Stanford University. He has completed his Ph.D. degree at Stanford University focusing on: synthesis (chemistry), properties (device physics) and applications (circuits) of carbon nanotube devices. From January 2010, he will be an Assistant Professor at University of Texas, Austin.

In his spare time, he practises wing chun kungfu and has taught for several years. He also enjoys western horse riding, and exploring religion and music.

Arash Hazeghi received his B.Sc. in Electrical Engineering with honors from University of Tehran in 2004 and his M.Sc. in Electrical Engineering in 2006 from Stanford University, Stanford, CA. Since 2006 he has been a Ph.D. candidate at Stanford, Department of Electrical Engineering. He is a member of the Wong Nanoelectronics Research Group at the Center for Integrated Systems, CIS. His research interests include carbon nanotubes (modeling and fabrication) as well as novel FET devices.

Li-Wen received her B.S. degree in Material Science and Engineering from National Tsing Hua University, Taiwan R.O.C. After graduating from Tsing Hua University, she worked at UMC, a semiconductor foundry, as a process integration engineer for 2 years. Her research interests are in semiconductor fabrication processes. She enrolled in Stanford University's Department of Material Science and Engineering in 2004 and is currently working with Prof. H.-S. Philip Wong on lithography subdivision using diblock copolymers.

SangBum Kim received his B.S. degree in Electrical Engineering from Seoul National University, Seoul, Korea, in 2001, and M.S. degree in Electrical Engineering from Stanford University in 2005. His research interests are in the design, characterization, and fabrication of new nonvolatile memory devices that need to be fast and power and space efficient. He is currently working on GST-based phase change memory.

Saeroonter received his B.S. degree in Electrical Engineering from KAIST (Korea Advanced Institute of Science and Technology), Daejeon, Korea, in 2004. His research interest is in nano-scaled III-V semiconductor material CMOS devices. He is now working on band-to-band tunneling measurements in pn junction diodes and device simulations, analysis on double-gate structure III-V material FETs.

Jenny received her B.S. degree in Electrical Engineering from UCSD (University of California San Diego) in La Jolla, California. At Stanford University, she is pursuing her M.S. degree in Electrical Engineering, and will continue for her Ph.D. Her research interests are in the fabrication and characterization of III-V CMOS devices. She is currently working on various gate dielectric materials.

Lan received her B. S. in Microelectronics and Economics from Peking University in 2005 and M. S. in Electrical Engineering from Stanford University in 2007. She is currently a Ph. D. candidate in Electrical Engineering at Stanford University, under Prof. H. –S. Philip Wong in Stanford Nanoelectronics Group. Her Ph.D. research focuses on technology scaling from a circuit-level and chip-level perspective, as well as integrated bio-system and biomedical devices. Lan enjoys exploring different cultures, people, places, and food, by traveling and reading.

Crystal received her B.S. Degrees in Engineering Physics and Computer Engineering as well as her M.S. Degree in Electrical Engineering from the University of Maine. She is currently a Ph.D. candidate in Electrical Engineering.

As conventional CMOS technologies scale the importance of implementing new materials and structures is becoming more apparent. III-V materials such as InGaAs show promise as "new" materials due to their high electron mobilities. Therefore it may prove beneficial to implement an NFET device with a III-V material as the channel. Ohmic contact technology will need to improve to effectively introduce these new devices at smaller technology nodes. Future work includes identifying and addressing the obstacles of ohmic contacts to III-V channel devices.

Marissa received her Sc.B. degree in Chemistry from Brown University in 2005. She is currently pursuing a Ph.D. in Chemistry at Stanford. Her research interests lie at the intersection of chemistry and electrical engineering and include phase change materials, nanoparticle synthesis and block copolymer self-assembly.

Research Topic: Future Non-volatile Memory Technology

Albert Lin received both his B.S. (2004) and M.Eng. (2006) in Electrical Engineering and Computer Science, with a minor in Biomedical Engineering, from the Massachusetts Institute of Technology. While at MIT, he was a recipient of a number of awards, including the Siebel Scholar Fellowship and Bell Northern Research Project Award, and a member of the American Academy of Achievement and several honor societies. In 2006, he received the Stanford Fellowship for Graduate Study at Stanford Electrical Engineering. He is currently a doctoral candidate under Prof. H.-S. Philip Wong of the Center for Integrated Systems.

Albert Lin joined the Stanford Nanotechnology Group (Wong Group) in 2007. His primary research is in carbon nanotube field effect transistor (CNFET) circuits, and includes some aspects of carbon nanotube (CNT) devices, modeling, and fabrication processes.

Jason Parker received his B.S. in Electrical Engineering and B.A. in German Language and Literature from the University of Washington in 2006. At Stanford, he is pursuing his M.S. and is a Ph.D. candidate in the Electrical Engineering department.

Jason's work focuses on incorporating silicon and germanium nanowires and carbon nanotubes into novel device structures. Specifically, he is working on nanowire solar cells as well as transistors that work around the fundamental subthreshold slope limit of 60 mV/dec.

Kyeongran Yoo joined the Stanford Nanoelectronics Group in 2007 after working with Applied Materials, Maydan Technology Center Group, Santa Clara, California. She is focusing on design, fabrication processes, and characterization of Nano-Electro Mechanical Systems (NEMS) including switches and memory devices.

As a process engineer at Applied Materials, she developed lithography processes for silicon based waveguide, high k gate transistors, and memory devices.

She received her B.S. degrees in Mathematics and Materials Engineering from Sungkyunkwan University, and M.S. degrees in Inorganic Materials Engineering from Seoul National University, Seoul, Korea and Materials Science Engineering, Stanford University, Stanford, California. Her MS thesis title was "Interdiffusion Behavior and Growth of InGaAs/InAlAs Multiple Quantum Wells (MQWs) using Low Pressure Metalorganic Chemical Vapor Deposition (LP-MOCVD).”

Cara Beasley received her B.S. in Chemistry from the University of California, Santa Barbara in 2005. She is currently pursuing a Ph.D. in Chemistry at Stanford. Currently, she is working on the chemistry behind carbon nanotube growth. She is looking at ways to tailor CVD growth to give specific diameter ranges, chiralities, and yeilds. Growths on different substrates is another topic of interest. She is working closely with other members of the group to fabricate CNT devices. In her spare time, Cara likes to ride horses, hike, raise chinchillas, and create stained glass windows.

Jiale Liang received her B.S. in Microelectronics from Peking University, China, in 2007. She is now pursuing her M.S. degree in Electrical Engineering at Stanford. Her research interests focus on device physics and modeling. Currently, she is working on the device physics of Carbon Nanotubes.

Helen received her BS degree in Condensed Matter Physics in 2007 from Nanjing University, China, and she is right now a PhD candidate in Stanford Physics Dept. Helen is interested in research concerning electron transport in CNT, contact between nanotubes and metal, and CNT interconnects.

Research Topic: NEMS from fabrication to circuit level design

Soogine Chong received her B.S. degree in Electrical Engineering from Seoul National University, Seoul, Korea, in 2003, and M.S. degree in Electrical Engineering from Stanford University in 2005. She is a receipient of Samsung Scholarship Foundation for her graduate work. Her research interests are in the design, characterization, and fabrication of NEMS switch with high endurance and also in the applications of NEMS, esp. SRAM through simulation.

Rakesh received his B.E degree in Electronics and Communication Engineering from Anna University, Chennai, India in 2005. He received his M.E in Microelectronics at the Indian Institute of Science, Bangalore, India in 2007. Since 2008 he is a Ph.D candidate at the Department of Electrical Engineering, Stanford University. His research interests include Non-volatile memory design and modeling with specific emphasis to Phase Change Memories. His past experiences include custom digital circuit design and high speed system design.

In his free time, Rakesh likes to go hiking, photography, music, religion, traveling and exploring different cultures.

Kokab Baghbani received her B.Sc. (2006) in Computer Engineering (Hardware) and her M.Sc. (2008) in Electrical Engineering (Semiconductor Devices) both from University of Tehran, Iran.
She works on CHIC project in Prof. Philip Wong group.
CHIC (CHip In Cell): In-situ detection of chemical changes in human body at the cellular level can bring enormous benefits in diagnosis and in therapeutic monitoring. We are developing techniques to place micron-sized sensor chip inside each cell. It might revolutionize biochemical imaging by introducing the idea of replacing “passive” radiotracers with “active” IC chips.

Graduated from Peking University, Beijing, China at year 2008 and received the B.S. degree in Microelectronics department. Now she is pursuing her M.S. degree at Electrical Engineering, Stanford University. Currently she is working on non-volatile resistance switching memory, metal oxide, e.g. NiO, Al2O3, to study the film properties and possible innovations to the memory structure.

Kerem Akarvardar received the B.S. and M.S. degrees from Istanbul Technical University (ITU), Istanbul, Turkey, in 1996 and 2000, the DEA degree from Joseph Fourier University, Grenoble, France, in 2003, and the Ph.D. degree from Grenoble Institute of Technology (INPG) in 2006. He was a Process Engineer with the National Research Institute of Electronics and Cryptology (UEKAE-YITAL), Kocaeli, Turkey, from 1996 to 2000. For his Ph.D., he was with the Institute of Microelectronics, Electromagnetism, and Photonics (IMEP), Grenoble. He is currently a Research Associate with the Electrical Engineering Department, Stanford University, Stanford, CA. His expertise is in the field of multiple-gate SOI FETs and NEMS-based logic and memory devices.

Dr. Xinyu Bao received his B.S. in physics from the University of Science and Technology of China in 2001. He received his Ph.D. in physics from the Institute of Physics, the Chinese Academy of Sciences (CAS) in 2006. From 2006 to 2008, he joined the Electrical and Computer Engineering Department at University of California, San Diego as a postdoctoral scholar. He is now working with Prof. H.-S. Philip Wong on the nanowire project at Stanford University.

Xinyu was awarded the Special Prize of President Scholarship for Postgraduate Students of CAS in 2006, the Outstanding Science and Technology Achievement Prize of CAS in 2005, and several fellowships. He has authored/co-authored papers in peer-reviewed journals, such as Science, Physical Review Letters, and Nano Letters. His research interests span a number of subjects based on low dimensional systems and currently focus on the growth, properties, and applications of nanowires.

Dr. Bae is from Samsung Electronics.
Visit period: September 2007 -

Rainer Bruchhaus is from Qimonda.
Visit period: August, 2007 - July 2010

Study of Chemistry and Mineralogy in Mainz and Munich, Germany
1983 PhD thesis in Inorganic Chemistry
1983 - 2000 Siemens Corporate Technology, ceramics and thin film technology, ferroelectric thin films for pyroelectric detector arrays
2001-2003 Infineon Technologies in Japan, FeRAM project with Toshiba in Yokohama
2004-2007 Conductive Bridge (CB)RAM project within Infineon/Qimonda

Current interests include phase change memory, CBRAM and resistive switching in transition metal oxides

Eiji Yoshida is from Fujitsu.
Visit period: August, 2007 -

Gael graduated in June 2008 with a PhD degree in Electrical Engineering from Stanford University.

During his time with the Nanoelectronics group, his research focused on carbon nanotube interconnects. His work culminated in the realization of the first integrated circuit with carbon nanotube interconnects and silicon transistors working above 1GHz. After graduation, he joined IBM Research in Zurich, Switzerland.

Yuan received her B.S. in Electronics from Peking University, China. During her undergraduate studies, she received a solid background in physics, circuits, devices and even math. In 2003, She was enrolled in the Electrical Engineering department at Stanford University, and had a chance to study towards the Ph.D. degree. She is currently a graduate student in nanotechnology. Her research interests focus on devices, especially non-volatile memory and nanowire devices.

Graduated 2007 with a Doctorate Degree in Electrical Engineering.

Jie received his B.S. degree in Electronics from Peking University, P.R.China, and the M.S. degree in Electrical Engineering from Stanford University. He reecived his Ph.D. degree in Electrical Engineering in 2007 from Stanford Univeristy in the Nanoelectronics Group directed by Prof. H.-S. Philip Wong. He worked on the circuit performance analysis of nanodevice logic arrays in terms of the circuit density, speed, power, and defect issues of fabricating arrays of nanoscale devices, and the performance benchmarking of carbon nanotube FETs with state-of-the-art Si CMOS technologies.

Ximeng Guan received his B.E. degree from the Department of Electronic Engineering, Tsinghua University, China in 2005. He is now a 4th-year Ph. D. candidate at the Institute of Microelectronics, Tsinghua University. Ximeng wasa visiting researcher to the Stanford Nanoelectronics Group from Jan. 2008 to Aug. 2008. He has authored/co-authored 15 conference/journal papers (including two 1st-author IEDM papers, one EDL paper and three SISPAD papers). His research interests include quantum transport simulation of CNT/GNR FETs, modeling of metal-semiconductor contact, molecular dynamics simulation of resistive memory, and bandstructure calculation for strained ultra-thin-bodies.

Dr. Sunae Seo was a visiting researcher the Samsung Advanced Institute of Technology, Korea.
Visit period: April, 2005 - April, 2006.

Dr. Jeong-Hyong Yi was a visiting scholar from Seoul National University, Korea.
Visit period: July, 2006 - July 2007.

Dr. Hae-Taek Kim was a visiting scholar from Kookmin University, Korea.
Visit period: August 2006 - August 2007.

Christoph Eggimann was a visiting scholar from EPFL (Prof. Adrian Ionescu's group), Switzerland from March 2007 - July 2007. While here, he focused on NEMS device modeling and fabrication. He is currently with Infineon Technologies, Munich, Germany.

Samuel Chang was an undergraduate research intern from National Taiwan University (NTU), Taiwan from June 2006 - August 2006. While here, he focused on improving the Schottky-Barrier carbon nanotube field effect transistor (CNFET) model such that it can be speedwise sufficient for VLSI CNFET circuit modeling. He is currently a graduate student in Electrical Engineering and Computer Science at the Massachusetts Institute of Technology. [Intern period: June, 2006 - August 2006]

Gordon Wan was with the Stanford Nanoelectronics Group from 2006-2008, when he worked on a variety of topics including CNTs and NEMS. He received his BS in Electrical Engineering and Mathematics, both with highest honors, from the University of Texas at Austin in 2005, and his MS in Electrical Engineering from Stanford University in 2007. He is currently pursuing his PhD in the Department of Electrical Engineering at Stanford University. While at the University of Texas at Austin, he was a recipient of a number of awards including the Silicon Laboratories Scholarship, Undergraduate Research Fellowships, and the Distinguished Honors Award for two times. In 2005, he received the James F. and Mary Lynn Gibbons Fellowship to attend graduate school at Stanford University. He has hold intern positions at Motorola Semiconductor Limited, Silicon Laboratories Inc, Intersil Corporation, and Qualcomm in 2002, 2004, 2006, and 2007 respectively.

He ranked 2nd in the Stanford University Electrical Engineering PhD Qualifying Exam and is a recipient of the Stanford Graduate Fellowship.