2009 VLSI Symposia
The 2009 VLSI Technology Symposium will be held on June 15-17 in Kyoto, Japan, where we will present three papers:
B. Lee, H.-S. P. Wong, “NiO Resistance Change Memory with a Novel Structure for 3D Integration and Improved Confinement of Conduction Path,” Symp. VLSI Technology, paper 9B-4, June 15 – 17, 2009, Kyoto, Japan.
M. Kobayashi, T. Irisawa, B. M. Kope, Y. Sun, K. Saraswat, H.-S. P. Wong, P. Pianetta, and Y. Nishi, “High Quality GeO2/Ge Interface Formed by SPA Radical Oxidation and Uniaxial Stress Engineering for High Performance Ge NMOSFETs,” Symp. VLSI Technology, paper 4B-2, June 15 – 17, 2009, Kyoto, Japan.
A. Lin, N. Patil, H. Wei, S. Mitra, and H.-S. P. Wong, “A Metallic-CNT-Tolerant Carbon Nanotube Technology Using Asymmetrically-Correlated CNTs (ACCNT),” Symp. VLSI Technology, paper 2B-3, June 15 – 17, 2009, Kyoto, Japan.