Stanford Nanoelectronics Lab

IEDM 2009

December 7, 2009

1. B.J. Bae, S. Kim, Y. Zhang, Y.K. Kim, I.G. Baek, S.O. Park, I.S. Yeo, S. Choi, J.T. Moon, H.-S. P. Wong, and K. Kim, “1D Thickness Scaling Study of Phase Change Material (Ge₂Sb₂Te₅) using a Pseudo 3-Terminal Device,” IEEE International Electron Devices Meeting (IEDM), paper 5.2, December 6 – 9, Baltimore, 2009.

2. D. Kuzum, T. Krishnamohan, A. Nainani, Y. Sun. P. A. Pianetta, H.-S. P. Wong, K. C. Saraswat, “Experimental Demonstration of High Mobility Ge NMOS,” IEEE International Electron Devices Meeting (IEDM), paper 19.1, December 6 – 9, Baltimore, 2009.

3. N. Patil, A. Lin, J. Zhang, H. Wei, K. Anderson. H.-S. P. Wong, S. Mitra, “VMR: VLSI-Compatible Metallic Carbon Nanotube Removal for Imperfection-Immune Cascaded Multi-Stage Digital Logic Circuits using Carbon Nanotube FETs,” IEEE International Electron Devices Meeting (IEDM), paper 23.4, December 6 – 9, Baltimore, 2009.

4. H. Wei, N. Patil, A. Lin, H.-S. P. Wong, S. Mitra, “Monolithic Three-Dimensional Integrated Circuits using Carbon Nanotube FETs and Interconnects,” IEEE International Electron Devices Meeting (IEDM), paper 23.5, December 6 – 9, Baltimore, 2009.

5. X. Chen, K.-J. Lee, D. Akinwande, G. Close, S. Yasuda, B. Paul, S. Fujita, J. Kong, H.-S. P. Wong, “High-Speed Graphene Interconnects Monolithically Integrated with CMOS Ring Oscillators Operating at 1.3GHz,” IEEE International Electron Devices Meeting (IEDM), paper 23.6, December 6 – 9, Baltimore, 2009.

6. L.-W. Chang, T.L. Lee, C. H. Wann, C.Y. Chang, H.-S. P. Wong, “Top-Gated MOSFETs with Diblock Copolymer Self-Assembled 20 nm Contact Holes,” IEEE International Electron Devices Meeting (IEDM), paper 36.3, December 6 – 9, Baltimore, 2009.

7. L. Wei, D. J. Frank, L. Chang, H.-S. P. Wong, “A Non-iterative Compact Model for Carbon Nanotube FETs Incorporating Source Exhaustion Effects,” IEEE International Electron Devices Meeting (IEDM), paper 37.7, December 6 – 9, Baltimore, 2009.