Publications

Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering

Authors	Deng, Jie; Wei, Lan; Chang, Li-Wen; Kim, Keunwoo; Chuang, Ching-Te; Wong, H.-S. Philip;
Date	April 23, 2008
Keywords	footprint, scaling, selective scaling, CMOS

How to Cite

J. Deng, L. Wei, L.-W. Chang, K. Kim, C.-T. Chuang, H.-S. P. Wong, "Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering," International Symposium on VLSI Technology, Systems and Applications, 2008 (VLSI-TSA 2008), pp. 159-160, Taiwan, 21-23 April 2008.

Abstract

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.

References

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8. S. Thompson, IEDM, p. 221, 2004.
9. N. Shah, M.S. Thesis, U. Florida, 2005.

Category

Nanoscale CMOS and III-V CMOS