Publications
Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits
| Authors | Nishant Patil, Jie Deng, Subhasish Mitra, and H.-S. Philip Wong |
| Date | January 16, 2009 |
| How to Cite | N. Patil, J. Deng, S. Mitra, H.-S. P. Wong, “Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits,” IEEE Trans. Nanotechnology, vol. 8, No. 1, pp. 37 - 45, 2009. |
| Abstract | Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related non-idealities and imperfections, and parasitic resistances and capacitances extracted from the CNFET circuit layout. We use Monte Carlo simulations using the CNFET SPICE model to investigate the effects of three major CNT process-related imperfections on circuit-level performance: 1) doping variations in the CNFET source and drain regions; 2) CNT diameter variations; and 3) variations caused by the removal of metallic CNTs. The simulation results indicate that metallic CNT removal has the most impact on CNFET variation; less than 8% of CNTs grown should be metallic to reduce circuit performance variation.This paper also presents an analytical model for the scalability of CNFET technology. High CNT density (250 CNTs/um) is critical to ensure that performance (delay and energy) gains over silicon CMOS are maintained or improved with shrinking lithographic dimensions. |
| Category | CNTs & CNFETs |