Log In / Register
Stanford Nanoelectronics Lab
  • Home
  • About Us
  • Presentations
  • Publications
  • Models
  • Media Gallery
  • Courses
  • Links
  • Featured Publications
  • Publication Index
  • Publication Categories
    • CNTs & CNFETs (32)
    • Nanoelectronics and Nanotechnology (14)
    • Nanoscale CMOS and III-V CMOS (19)
    • NEMS-Based Logic and Memory (6)
    • PCM & Diblock Copolymer (17)
    • Additional Publications (2)

Publications

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory

Download Publication
Currently Unavailable
Authors Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong
Date June 12, 2007
How to Cite Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, “An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory,” Symp. VLSI Technology, pp. 98 – 99, June 12 – 14, 2007, Kyoto, Japan.
Abstract We demonstrate a novel phase change memory cell utilizing doped nanowire pn-junction diode both as a bottom electrode and a memory cell selection device for a cross-point memory array. Using an isolated vertical nanowire in each cell, the contact area is below the lithography limit. Very low SET programming current of 30 uA is achieved. RESET/SET resistance ratio is 100x. The diode provides 100x isolation between forward and reverse bias in the SET state.
Category PCM & Diblock Copolymer
  • Terms of Use
  • Administrator Login
Copyright © 2008 Stanford University Contact the Webmaster