Publications

Integrated Wafer-Scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures

We successfully demonstrate essential components and their integration for large-scale Carbon Nanotube Field Effect Transistor (CNFET) technology: 1. First demonstration of full-wafer-scale growth of directional carbon nanotubes (CNTs) on 4” single-crystal quartz wafers. 2. First demonstration of full-wafer-scale CNT transfer from 4” quartz wafers to 4” silicon wafers for integration on silicon. 3. Integration of full-wafer-scale growth and transfer, together with metallic-CNT removal, for the first demonstration of misaligned-CNT-immune digital logic structures on a full-wafer-scale. Such logic structures guarantee correct logic functionality in the presence of a large number of misaligned and mis-positioned CNTs.

Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.

Carbon Nanotube Transistor Compact Model for Circuit Design and Performance Optimization

In this paper, we describe the development of the Stanford University Carbon Nanotube FET (CNFET) Compact Model. The CNFET Model is a circuit-compatible, compact model which describes enhancement-mode, CMOS-like CNFETs. It can be used to simulate both functionality and performance of large-scale circuits with hundreds of CNFETs. To produce realistic and relevant results, the model accounts for several practical non-idealities such as scattering in the near-ballistic channel, effects of the source/drain extension region, and charge-screening for multiple-nanotube CNFETs. The model also includes a full transcapacitance network for more accurate transient and AC results. The Stanford University CNFET Model is implemented in both HSPICE macro language and VerilogA. The VerilogA implementation shows speedups of roughly 7x∼15x over HSPICE. Applications of the model suggest that n- and p-CNFETs will have 6x and 13x speed advantage over Si n- and p-MOSFETs respectively at the 32nm node, and that a CNT density of 250 CNTs/um is ideal for multiple-nanotube gates. Such a compact CNFET model will be absolutely essential in ushering in the Design Era of CNFET circuits as carbon nanotube technology outgrows its “science discovery” phase.

An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory

We demonstrate a novel phase change memory cell utilizing doped nanowire pn-junction diode both as a bottom electrode and a memory cell selection device for a cross-point memory array. Using an isolated vertical nanowire in each cell, the contact area is below the lithography limit. Very low SET programming current of 30 uA is achieved. RESET/SET resistance ratio is 100x. The diode provides 100x isolation between forward and reverse bias in the SET state.

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance C_gg is decomposed into three major components: 1) capacitance C_gc between the gate and the parallel cylindrical conducting channels (the number of channels >= 1) in dual-layer dielectric materials; 2) outer fringe capacitance C_of between the gate and the source/drain cylinder conductors; and 3) coupling capacitance C_gtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed.

Analysis of the Frequency Response of Carbon Nanotube Transistors

The characterizations of carbon nanotube transistors at high frequencies have so far been hindered by large parasitic and extrinsic capacitances. We present a quantitative analysis of the limitations imposed by probe pad parasitics on single-wall carbon nanotube transistor characterization at gigahertz frequencies. Our analysis reveals the various kinds of frequency responses that can be expected to be measured. Furthermore, we present design guidelines and a suitable device layout to achieve gain and bandwidth at gigahertz frequencies.

An Analytical Derivation of the Density of States, Effective Mass and Carrier Density of Achiral Carbon Nanotubes

An analytical electron density of states (DOS) for zigzag and armchair single-wall carbon nanotubes (CNTs) are derived in this paper. The derivation originates from the tight-binding energy dispersion relation for CNTs and reveals the essential physics such as periodic van-Hove singularities and its dependence on chirality. The DOS derivation is exact and contains no additional approximations or assumptions, except those inherent in the nearest neighbor tight-binding model. In addition, we derive analytical expressions for the group velocity, effective mass, and nondegenerate equilibrium carrier density.

A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.