Publications

Finite Element Analysis and Analytical Simulations of Suspended Gate-FET for Ultra-low Power Inverters

This paper proposes, the investigation of the Suspended Gate Field-Effect Transistor (SG-FET) small-slope switch based on a hybrid numerical simulation approach combining ANSYSTM Multiphysics and ISE-DESSISTM in a self-consistent system. The proposed numerical simulations uniquely enable the investigation of the behavior and the physics of complex micro-electro-mechanical/solid-state devices, such as the SG-FET. Abrupt switching as well as the effect of trapped charges in the gate dielectric are demonstrated. The numerical data serve to calibrate an analytical EKV-based SG-FET model, which is then used to design and originally simulate a sub-micron (90 nm) scaled SG-FET complementary inverter. It is shown that, due to abrupt switching in the subthreshold region and electro-mechanical hysteresis, the SG-FET inverter could deliver a significant power saving (1–2 decades reduction of inverter peak current and practically no leakage power) compared to traditional CMOS inverter.

Energy-Reversible Complementary NEM Logic Gates

Energy-reversible complementary nanoelectromechanical (ER CNEM) logic gates are introduced. For the same delay, ER CNEM gates can operate at much lower supply voltages relative to conventional (CMOS-like) CNEM gates and their reliability is significantly higher.

Numerical and Analytical Simulations of Suspended Gate FET for Ultra-Low Power Inverters

This paper proposes, for the first time, the investigation of the SG-FET small slope switch based on a
hybrid numerical simulation approach combining ANSYS™ Multiphysics and ISE-DESSIS™ in a self-consistent system. The proposed hybrid numerical simulations uniquely enables the investigation of the physics of complex Micro-Electro-Mechanical/solid-state devices, such as SG-FET. Abrupt switching and effect of gate charges are demonstrated. The numerical data serves to calibrate an analytical EKV-based SG-FET model, which is the used to design and originally simulate a sub-micron (90nm) scaled SG-FET complementary inverter. It is demonstrated that, due to abrupt switch in the subthreshold region and electro-mechanical hysteresis, the SGFET inverter provides significant power saving (1-2 decades
reduction of inverter peak current and practically, no leakage power) compared with traditional CMOS inverter.

Analytical Modeling of the Suspended-gate FET and Design Insights for Low Power Logic

An analytical model for the suspended-gate field-effect transistor (SGFET), dedicated to the dc analysis of SGFET logic circuits, is developed. The model is based on the depletion approximation and expresses the pull-in voltage, the pull-out voltage, and the stable travel range as a function of the structural parameters. Gate position is explicitly expressed as a function of the gate voltage, thus enabling the convenient integration of the analytical SGFET relationships into the standard MOSFET models. Starting from the new SGFET model, the influence of the mechanical hysteresis on the circuit steady-state behavior is discussed, the potential of using the SGFET as an ultra-low power switch is demonstrated, and the operation of the complementary SGFET inverter is analyzed.

Design considerations for complementary nanoelectromechanical logic gates

The operation and performance of complementary nanoelectromechanical (CNEM) logic gates are investigated. NEMS structures featuring dimensions 2 to 3 orders of magnitude smaller than the present MEMS relays are considered. Various metals are benchmarked to silicon as the cantilever beam material. We show that the CNEM inverters featuring laterally actuated beams, 10 nm gap and low density materials such as Si or Al can achieve nanosecond pull-in delay and sub-0.1 fJ switching energy at VDD = 1.5 V while occupying an area as small as 0.03 μm2.

Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic

We present a new, analytical model for the SGFET that is suitable for hand calculations and time-efficient circuit simulations. Our model expresses the pull-in, pull-out voltages and the stable travel range in terms of the structural parameters and the moving gate position as a function of the gate voltage. Starting from our model, we discuss the influence of the structural parameters on the transistor characteristics and the potential of the SGFET for logic circuits. We also introduce the SGFET SRAM cell to demonstrate the use of our model and to illustrate the interest of the SGFET for ultra-low power applications. SGFET logic gates exhibit a significantly reduced off-state power dissipation and improved functionality as compared to CMOS gates.