Publications

Fabrication and Characterization of Emerging Nanoscale Memory

Conventional solid state memory technologies such as flash memory, DRAM, and SRAM are facing scaling challenges due to fundamental limitations. Therefore, various new memory technologies are being widely researched and evaluated to continue the cost/performance improvement trend of solid state memory devices. To assess the potential scalability of emerging nanoscale memory beyond conventional limits, it is essential to characterize and understand how differently they perform at the nanoscale compared to known properties in the microscale. New nanoscale fabrication methods and new memory technologies offer a great opportunity for future memory device research. In this regard, we evaluated characteristics of nanoscale phase change memory and Ni oxide memory using nanofabrication technologies such as nanowire growth, nanocrystal synthesis, diblock copolymer patterning, and ebeam lithography. Evaluated characteristics include not only their device performance but also key material properties that might affect the ultimate device performance. The nanofabrication method for each memory material is also discussed due to its potential to overcome the difficulties of conventional semiconductor fabrication process.

Modeling and Performance Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and Screening Effect

Devices based on nanotubes and nanowires have been a popular research topic in the recent years. Many groups have shown promising experimental results in this area. In this paper, we examine the expected performances of 1-D and 2-D MOSFETs by numerical simulation and analytical models. We show that 1-D devices are not necessarily better than 2-D devices for future technologies, especially for low-channel densities and narrow gate widths, due to the parasitic capacitances and screening of the adjacent channels. For example, the delay improvement is overestimated from the intrinsic cases by at least 30%-60% from ignoring parasitics and channel screening effects, for Wgate<10 Lg and channel densities from 400 to 25 mum. We propose a methodology for 1-D device design optimization, and a possible scaling path of 1-D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1-D FETs.

The End of CMOS Scaling: Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance

The rapid cadence of metal-oxide semiconductor field-effect transistor (MOSFET) scaling, as seen in the new 2003 International Technology Roadmap for Semiconductors ITRS), is accelerating introduction of new technologies to extend complementary MOS (CMOS) down to, and perhaps beyond, the 22-nm node. This acceleration simultaneously requires the industry to intensify research on two highly challenging thrusts: one is scaling CMOS into an increasingly difficult manufacturing domain well below the 90-nm node for high performance (HP), low operating power (LOP), and low standby power (LSTP) applications, and the other is an exciting opportunity to invent fundamentally new approaches to information and signal processing to sustain functional scaling beyond the domain of CMOS. This article is focused on scaling CMOS to its fundamental limits, determined by manufacturing, physics, and costs using new materials and nonclassical structures. This paper provides a brief introduction to each of the new nonclassical CMOS structures. This is followed by a presentation of one scenario for introduction of new structural changes to the MOSFET to scale CMOS to the end of the ITRS. A brief review of electrostatic scaling of a MOSFET necessary to manage short channel effects (SCEs) at the most advanced technology nodes is also provided.

Nanoelectronics – Opportunities and Challenges (IJHSES)

As device sizes approach the nanoscale, new opportunities arise from harnessing the physical and chemical properties at the nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper will give an overview of the materials, technology, and device opportunities in the nanoscale era. So far, much of the nanoscale sciences have been researched in the physics, chemistry, and materials science communities. While there have been plenty of good science in the nano world, nanotechnology is still at its infancy. The engineering community is poised to make a major impact in transforming good nanoscience into useful nanotechnology. The disciplined performance benchmarking against alternatives as practiced by the engineering community will prove to be invaluable to the development of new nanotechnologies. Examples of such performance benchmarking exercises will be shown and directions for future work will be suggested.

Nanodevices Beyond Silicon: Device and Circuit Implications

In this paper, we survey the salient characteristics of nanodevices beyond "silicon CMOS". Carbon nanotubes, semiconductor nanowires, and devices made of molecules are discussed as examples. New devices may have characteristics different from conventional Si CMOS. We discuss the circuit implications of these new devices. Opportunities offered by new fabrication techniques such as self-assembly may enable device fabrication beyond the lithographic limit. An example of new circuit architecture based on sublithographic nanodevice array is described.

Nanoelectronics: Opportunities and Challenges (WOFE)

Nanotechnology Overview

Nanoelectronics: Opportunities and Challenges (AVS)

Nanoelectronics: Nanotubes, Nanowires, Molecules, and Novel Concepts

As device sizes approach the nanoscale, new opportunities arise from harnessing the physical and
chemical properties at the nanoscale. Chemical synthesis, self-assembly, and templated self-assembly promise the precise fabrication of device structures or even the entire functional entity. Quantum phenomena and onedimensional transport may lead to new functional devices with very different power/performance tradeoffs. New materials with novel electronic, optical, and mechanical properties emerge as a result of the ability to manipulate matter on a nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper will give an overview of the materials, technology, and device opportunities in the nanoscale era. The focus of discussion will be on nanotubes, nanowires, molecular devices, and novel device concepts for nanoelectronics.

Device Opportunities of Nanotechnology

Nanotechnology for the Semiconductor Industry

Emerging Memories

Beyond the Conventional Transistor

Recent progress in continuing CMOS scaling is accomplished by introducing new device structures and new materials. This paper reviews recent progress in new technology features for silicon CMOS. With the imminent perceived “end” of CMOS device scaling, there is renewed interest in other non-silicon-FET based device and system architectures. We will discuss the merits of various proposed devices and fabrication techniques and suggest areas for further study.

Nanoelectronics - Opportunities and Challenges (IJHSES)

As device sizes approach the nanoscale, new opportunities arise from hamessing the physical and chemical properties at the nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper will give an overview of the materials, technology, and device opportunities in the nanoscale era. So far, much of the nanoscale sciences have been researched in the physics, chemistry, and materials science communities. While there have been plenty of good science in the nano world, nanotechnology is still at its infancy. The engineering community is poised to make a major impact in transforming good nanoscience into useful nanotechnologv. The disciplined performance benchmarking against alternatives as practiced by the engineering community will prove to be invaluable to the development of new nanotechnologies. Examples of such performance benchmarking exercises will be shown and directions for future work will be suggested.