Publications

CMOS technology roadmap projection including parasitic effects

In this paper, we revisit the Si CMOS roadmap projection by taking into consideration the parasitic capacitances, which significantly affect the device performance beyond 32nm technology. Capacitance components are analytically modeled and different design rules are examined.

Effect of Parasitic Resistance and Capacitance on Performance of InGaAs HEMT Digital Logic Circuits

The impact of parasitic resistance and capacitance on InGaAs HEMT digital logic circuits is investigated
via device simulations and circuit analysis. We present the correlation between device geometry and circuit delay for various structural scenarios. When the gate-to-S/D contact distance Lsg is scaled down to logic device standards, high integration density and additional circuit performance can be expected as compared with experimental devices that are demonstrated to date. This work highlights the importance of engineering the device structure outside the channel region to achieve high device performance and device density. Scaled InGaAs HEMTs show superior performance over experimental devices and 27% less power consumption for the same circuit-speed constraint.

Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-$kappa$/metal gate) reach their limits and physical gate length can no longer be effectively scaled down. By judiciously engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of selective device structure scaling that will enable technology scaling and contacted gate pitch scaling for several generations beyond the currently perceived limits.

Physics-Based Compact Model of III-V Heterostructure FETs for Digital Logic Applications

A physics-based analytical compact model of InGaAs FETs for logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures SCE, trapezoidal well QW energies and capacitances including 2D potential profile information.

Fermi-Level Depinning of GaAs for Ohmic Contacts

A novel non-alloyed contact structure for n-GaAs is introduced by using Al as a low workfunction metals in combination with a depinned Fermi level. The metal/GaAs Fermi level is depinned by inserting an ultrathin insulator between the metal and semiconductor to reduce the charging of metal induced gap states (MIGS). Fermi level depinning is verified through modulation of the effective Schottky barrier height by metal workfunction and insulator thickness. We expect this method can be used to make scalable low resistance ohmic contacts for III-V MOSFET/HEMTs, and tunable barrier heights for Schottky Barrier FETs.

Hole Mobility Characteristics under Electrical Stress for Surface-Channel Germanium Transistors with High-k Gate Stack

This paper describes device degradation and mobility characteristics for germanium (Ge)-channel p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) with HfO2 gate dielectrics. In order to understand the effect of trapped charges in high permittivity (high-κ) gate dielectric and interface-trap states, we compare the hole mobility of the SiGe/SiO2/Si (SGOI) structure before and after applying an electrical stress. It is found that hot-carrier injection (HCI) and constant–voltage Fowler–Nordheim (F–N) stress cause mobility degradation in different mechanism. Even a negative-biased moderate F–N stress will give recovery of hole mobility. These results indicate that the device performance of a surface-channel SGOI device is easily affected by the specific trapped-charge state in high-κ dielectrics and interface traps.

Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering

We propose a path for extending the technology roadmap when currently considered technology boosters (e.g., strain, high-k/metal gate) reach their limits. By carefully engineering the device parasitic resistance and parasitic capacitance, and considering the impact of the interconnect wiring capacitance, we propose scenarios of device footprint and device structure scaling that will enable technology scaling for several generations beyond the currently perceived limits.

Effective Drive Current for Sub-45nm Technologies

We propose a new model for the effective drive current (Ieff) of CMOS inverters, where the maximum FET current obtained during inverter switching (Ipeak) is a key parameter. Ieff is commonly defined as the average between IH and IL, where IH=Ids(Vgs=Vdd, Vds=0.5Vdd) and IL = Ids(Vgs=0.5Vdd, Vds=Vdd). In the past, this Ieff definition has been accurate in modeling the inverter delay. However, we find that as devices are scaled further into the nanoscale regime, the maximum transient current can deviate severely from IH, in which case, another metric should be used. The deviation of Ipeak from IH is found to increase as delay decreases or as device overdrive voltage increases. We define Ieff = (Ipeak+IM+IL)/ 3, where IM = Ids(Vgs=0.75Vdd, Vds=0.75Vdd). We evaluate our model against others by comparing the analytical and HSPICE extracted Ieff ratios across devices of varying threshold voltages, VTH. Our model is shown to better capture changes in VTH/Vdd, which are important since Vdd has not been scaled much, while VTH still remains a design parameter for the sub-45nm technologies.

Investigation of Performance limits of III-V Double-Gate n-MOSFETs

The performance limits of ultra-thin body double-gated (DG) III-V channel MOSFETs are presented in this paper. An analytical ballistic model including all the valleys (6-, X- and L-), was used to simulate the source to drain current. The bandto-band tunneling (BTBT) limited off currents, including both the direct and the indirect components, were simulated using TAURUSTM. Our results show that at significantly high gate fields, the current in the III-V materials is largely carried in the heavier L-valleys than the lighter 6- valleys, due to the low density of states (DOS) in the 6, similar to current conduction in Ge. Moreover, these high mobility materials like InAs, InSb and Ge suffer from excessive BTBT which seriously limits device performance. Large bandgap III-V materials like GaAs exhibit best performance due to an ideal combination of low conductivity effective electron mass and a large bandgap.

Circuit Analysis of Sublithographic Nanodevice Logic Array

Nanoscale devices (cross-point molecular diodes and nanowire/nanotube FETs) can
be arranged in a cross array. The results from C.T. Black et al. from IBM [1]
illustrated the use of Lithography Subdivision. The self-assembled diblock
copolymers can be used as an etch mask to generate the dielectric hard mask for
pattern formation by etching. In this way, the lithography features can be further
sub-divided by the self-assembly process. To achieve ultra-high device density, the
nanodevices array can be made with a sublithographic half-pitch (Fs) much smaller
than the lithography half-pitch (F) using self assembly method. Configuring
nanodevices on a regular grid may be the only way to fabricate nanodevices beyond
the lithographic limit.

In this paper, we implemented circuit functions using both customer-programmable
logic array and gate-mask programmable logic array made with Carbon Nanotube
(CNT). Compared to the crossed-wire array [2], only one dimension of our circuits is
defined by sublithographic half pitch which can be fabricated with lithography
subdivision by templated assembly, and the other dimension is defined by
conventional photolithography. We compared circuit density of this new approach
with the densest ROM cell made with the state-of-the-art CMOS process. We also
implemented a compact circuit-compatible device model for Carbon Nanotube
Field-Effect-Transistor (CNFET) to do the speed/power performance comparison
between sublithographic array logic and 45nm CMOS random logic, function to
function.

Theoretical Investigation Of Performance In Uniaxially- and Biaxially-Strained Si, SiGe, and Ge Double-Gate p-MOSFETs

Using the non-local empirical pseudopotential method (bandstructure), full-band Monte-Carlo simulations (transport), 1D Poisson-Schrodinger (electrostatics) and detailed band-to-band-tunneling (BTBT) (including bandstructure and quantum effects) simulations, the effect of uniaxial- and biaxial-strain, band-structure, mobility, effective masses, density of states, channel orientation and high-field transport on the drive current, off-state leakage and switching delay in nano-scale, Si, SiGe and Ge, p-MOS DGFETs is thoroughly and systematically investigated.

Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI

We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultra-thin body (UTB) fully-depleted SOI (FD-SOI) transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2-D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier.

Advanced CMOS Devices – A Tutorial From Practical Options to Innovative Concepts: Part II – Exploratory Devices and Approaches

Also see
http://www.electrochem.org/meetings/biannual/207/abstracts/tp/reportTechProg_501_K1.html

Advanced CMOS Devices – A Tutorial From Practical Options to Innovative Concepts: Part I – Conventional Devices and Technology Options

Also see
http://www.electrochem.org/meetings/biannual/207/abstracts/tp/reportTechProg_501_K1.html

Research Opportunities for Nanoscale CMOS

Device and Technology Challenges for Nanoscale CMOS

With the introduction of 90 nm node technology, silicon CMOS is already at the nanoscale. There is no doubt that the semiconductor industry desires to stay on the historical rate of cost/performance/density improvement as exemplified by the International Technology Roadmap for Semiconductors (ITRS). The challenges for continued device scaling are daunting. At the highest level, the challenges are: (1) delivering cost/performance improvement while at the same time containing power consumption/dissipation, (2) control of device variations, and (3) device/circuit/system co-design and integration. New devices and new materials offer new opportunities for solving the challenges of continued improvement. In this talk, we give an overview of the device options being considered for CMOS logic technologies from 45 nm to 22 nm and beyond. Technology options include the use of device structures (multi-gate FET) and transport-enhanced channel materials (strained Si, Ge). Beyond the 22 nm node, research are underway to explore even more adventurous options such as III-V compound semiconductors as channel materials, metal Schottky source/drain. Beyond that time horizon, there is the question of whether new materials and fabrication methods such as carbon nanotubes, semiconductor nanowires and self-assembly techniques will make an impact in nanoscale CMOS technologies. We survey the state-of-the-art of these emerging devices and technologies and discuss the research opportunities going forward. We conclude with a discussion of the interaction between device design and the circuit/system architecture and how this interaction will change the landscape of technology development in the future.

High Mobility Materials and Novel Device Structures for High Performance n-MOSFETs

The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology

We propose selective scaling of device footprint for 65 nm and beyond CMOS technologies. The benefits of selective scaling of device footprint are illustrated using an ultrathin-body fully depleted silicon-on-insulator transistor as an example. We study the effect of footprint scaling on device, circuit, and system level performance. A complete 2-D device structure is modeled for the numerical analysis. The results predict that an optimal footprint design can provide 30% smaller chip layout area, 20% faster speed, and 10% less dynamic power on overall chip performance benchmarked with a 53-bit pipelined multiplier. The variability analysis on both DC and AC characteristics indicates that the benefits of selective footprint scaling are not degraded by device variation.

1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect

This paper studies the parasitic capacitance of 1-dimensional (1D) and 2-dimensional (2D) MOSFETs by numerical simulation and analytical models. We show that 1D devices are not necessarily the better choice over 2D devices for future technologies, especially for low channel densities and narrow gate widths. For Wgate<10Lg, the delay improvement is overestimated from the intrinsic case by at least 30%-60% from ignoring parasitics and channel screening effects, for channel density from 400/um-25/um. A methodology for 1D device design optimization is proposed, followed by a possible scaling path of 1D devices down to 11 nm node. The analytical model is a first step toward a compact model for 1D FETs.