Publications

Effects of carbon source geometry and reactivity on the CVD growth of single-walled carbon nanotubes

Carrier Density and Quantum Capacitance for Semiconducting Carbon Nanotubes

A full-band analytical model of the equilibrium carrier density for single-wall semiconducting carbon nanotubes (sCNTs) is presented. The carrier density, which is a fundamental property of all semiconductors, is obtained using a semiempirical method for degenerate positions of the Fermi level and shows good agreement with numerical tight-binding results. The quantum capacitance is subsequently derived from the carrier density and used to develop a C-V model with good agreement with experimental quantum capacitance measurements. An analytical model of the gate coupling function of sCNTs is also reported which relates the internal surface potential with the external applied gate voltage. The diameter temperature and Fermi level dependency, and the essential properties of CNT device physics are captured in these analytical equations.

An Analytical Model for Intrinsic Carbon Nanotube FETs

A simple and efficient model of carbon nanotube field effect transistor (CNFET) is necessary to perform system-level optimization. In this paper, an analytical model with no iteration or integration is developed, including an analytical electrostatic model for the surface potential and simplification of scattering effects. The model is computationally efficient, but includes essential physics such as DIBL effect and scattering.

Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit

Due to their excellent electrical properties and small size, metallic carbon nanotubes (CNTs) are promising materials for interconnect wires in future integrated circuits. Indeed, simulations have firmly established CNTs as strong contenders for replacing or complementing copper interconnects. In this paper, we analyze the performances of a prototype 0.25-mum CMOS digital integrated circuit with select horizontal multiwall CNT (MWCNT) interconnects. Some local interconnect wires of the prototype chip were implemented, during a post-CMOS assembly process, by single 14-mum -long metallic MWCNT with 30-nm diameter, representative of future requirements for local interconnects. We evaluate the merits and challenges of MWCNT interconnects in a realistic silicon integrated-circuit environment. We experimentally extract the subnanosecond delays of these wires to quantitatively benchmark their future potential for the first time. Furthermore, we compare our experimental results with an existing MWCNT interconnect model, as well as with the expected performances of scaled copper wires. Finally, we discuss the origin of the discrepancies between our experimental results and the modeling projections.

CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes

Massive aligned carbon nanotubes hold great potential but also face significant integration/assembly challenges for future beyond-silicon nanoelectronics. We report a wafer-scale processing of aligned nanotube devices and integrated circuits, including progress on essential technological components such as wafer-scale synthesis of aligned nanotubes, wafer-scale transfer of nanotubes to silicon wafers, metallic nanotube removal and chemical doping, and defect-tolerant integrated nanotube circuits. We have achieved synthesis of massive aligned nanotubes on complete 4 in. quartz and sapphire substrates, which were then transferred to 4 in. Si/SiO2 wafers. CMOS analogous fabrication was performed to yield transistors and circuits with features down to 0.5um, with high current density ~20 uA/um and good on/off ratios. In addition, chemical doping has been used to build fully integrated complementary inverter with a gain ~5, and a defect-tolerant design has been employed for NAND and NOR gates. This full-wafer approach could serve as a critical foundation for future integrated nanotube circuits.

Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs

In this paper, we demonstrate postprocessing techniques to adjust the threshold voltage (Vt ) and on–off ratio (I_ON/I_OFF) of multiple-tube carbon nanotube field effect transistors (CNFETs). These postprocessing techniques open up an additional degree of freedom to further tune individual CNFETs in addition to various device synthesis and processing techniques. We demonstrate proof-of-concept experiments and fully characterize their design spaces and tradeoffs. The techniques, Threshold Voltage Setting and On–Off Ratio Tuning, were able to adjust the threshold by as much as 2 V and tune the on–off ratio across 5 × 10^3 to 5 × 10^5 . In addition, Vt Setting could be used as an analysis tool to infer the Vt distribution of grown carbon nanotubes (CNTs). These tuning techniques, combined with processes such as doping, will enable high-performance multiple-nanotube devices.

Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits

Carbon nanotubes (CNTs) show great promise as extensions to silicon CMOS due to their excellent electronic properties and extremely small size. Using a Carbon Nanotube Field Effect Transistor (CNFET) SPICE model, we evaluate circuit-level performance of CNFET technology in the presence of CNT fabrication-related non-idealities and imperfections, and parasitic resistances and capacitances extracted from the CNFET circuit layout. We use Monte Carlo simulations using the CNFET SPICE
model to investigate the effects of three major CNT process-related imperfections on circuit-level performance: 1) doping variations in the CNFET source and drain regions; 2) CNT diameter variations;
and 3) variations caused by the removal of metallic CNTs. The simulation results indicate that metallic CNT removal has the most impact on CNFET variation; less than 8% of CNTs grown should be metallic to reduce circuit performance variation.This paper also presents an analytical model for the scalability of CNFET technology. High CNT density (250 CNTs/um) is critical to ensure that performance (delay and energy) gains over silicon CMOS are maintained or improved with shrinking lithographic dimensions.

Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits

Carbon-nanotube (CNT) field-effect transistors (CNFETs) are promising extensions to silicon CMOS. Simulations show that CNFET inverters fabricated with a perfect CNFET technology have 13 times better energy delay product compared with 32-nm silicon CMOS inverters. The following two fundamental challenges prevent the fabrication of CNFET circuits with the aforementioned advantages: 1) misaligned and mispositioned CNTs and 2) metallic CNTs. Misaligned and mispositioned CNTs can cause incorrect functionality. This paper presents a technique for designing arbitrary logic functions using CNFET circuits that are guaranteed to implement correct functions even in the presence of a large number of misaligned and mispositioned CNTs. Experimental demonstration of misaligned and mispositioned CNT-immune logic structures is also presented.

Integrated Wafer-Scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures

We successfully demonstrate essential components and their integration for large-scale Carbon Nanotube Field Effect Transistor (CNFET) technology: 1. First demonstration of full-wafer-scale growth of directional carbon nanotubes (CNTs) on 4” single-crystal quartz wafers. 2. First demonstration of full-wafer-scale CNT transfer from 4” quartz wafers to 4” silicon wafers for integration on silicon. 3. Integration of full-wafer-scale growth and transfer, together with metallic-CNT removal, for the first demonstration of misaligned-CNT-immune digital logic structures on a full-wafer-scale. Such logic structures guarantee correct logic functionality in the presence of a large number of misaligned and mis-positioned CNTs.

Carbon Nanotube Transistor Compact Model for Circuit Design and Performance Optimization

In this paper, we describe the development of the Stanford University Carbon Nanotube FET (CNFET) Compact Model. The CNFET Model is a circuit-compatible, compact model which describes enhancement-mode, CMOS-like CNFETs. It can be used to simulate both functionality and performance of large-scale circuits with hundreds of CNFETs. To produce realistic and relevant results, the model accounts for several practical non-idealities such as scattering in the near-ballistic channel, effects of the source/drain extension region, and charge-screening for multiple-nanotube CNFETs. The model also includes a full transcapacitance network for more accurate transient and AC results. The Stanford University CNFET Model is implemented in both HSPICE macro language and VerilogA. The VerilogA implementation shows speedups of roughly 7x to 15x over HSPICE. Applications of the model suggest that n- and p-CNFETs will have 6x and 13x speed advantage over Si n- and p-MOSFETs respectively at the 32nm node, and that a CNT density of 250 CNTs/um is ideal for multiple-nanotube gates. Such a compact CNFET model will be absolutely essential in ushering in the Design Era of CNFET circuits as carbon nanotube technology outgrows its “science discovery” phase.

Fabrication and Characterization of Carbon Nanotube Interconnects

We have fabricated arrays of individual metallic multi-wall carbon nanotube interconnects. We have also collected about two hundred resistance measurements to compare four different contact metals: Al, Au, Ti and Pd. Au and Pd contacts gave the lowest resistance. To validate the concept of high-speed carbon nanotube (CNT) interconnect, we have extended our electrical measurements of individual multi-wall
carbon nanotubes (MWCNTs) into the radio-frequency regime up to 15 GHz. We also discuss the reasons why the conductivity of commercial MWCNTs is not yet competitive with copper.

Metric of Performance Benchmarking of Nanoscale Si and Carbon Nanotube FET

A commonly used FET performance metric is the gate delay metric CLoadVDD/I, where
I is the saturation on-current (IDsat=IDS@VGS=VDS=VDD). As CMOS continues to scale
deeper into the nanoscale, various device non-idealities cause the I-V characteristics
to be substantially different from well-tempered MOSFETs. The I-V characteristics of
these novel devices, while they appear deceptively similar, are not scaled versions of
the Si FET. In order to properly benchmark future nanoscale Si FETs and novel FET
such as CNFETs, it is necessary to develop a benchmarking metric that takes into
account of the shape of the I-V characteristics with the device operated in a circuit
environment.

This paper proposes a simple and accurate expression for inverter effective drive
current for nanoscale Si and carbon nanotube FET (CNFET) performance
benchmarking. The choice of Ieff = (INL + INH + IP)/2, where INL = IDS(N-FET)
(VGS=0.5VDD, VDS=VDD), INH = IDS(N-FET) (VGS=0.8VDD, VDS=0.5VDD), IP = IDS(P-FET)
(VSG=0.2VDD, VSD=0.5VDD), includes the effects of both the nFET and the pFET of
an inverter, and accurately captures the inverter delay performance over many CMOS
technology nodes and novel FETs. The proposed metrics indicate that the
performance enhancement of CNFETs over Si CMOS is not as large as that predicted
by IDsat in a circuit environment because of the non-ideal IV characteristics.

Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling (IEEE NANO)

The theoretical performance of Carbon Nanotube Field Effect Transistors (CNFETs) with Schottky barriers is examined by means of a ballistic model. A novel approach is used to treat the Schottky barriers at the metal-nanotube contacts as mesoscopic scatterers. Evanescent-mode analysis is used to derive a length-scale and potential profile for the device. Noticeable current reduction is observed compared to previous ballistic models without Schottky barriers. The effects of device geometry, nanotube diameter and chirality as well as Schottky barrier height on the drain current are studied. Quantum conductance degradation due to Schottky barriers is also observed.

A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors

This paper presents a circuit-compatible compact model for short channel length (5nm~100nm), quasi-ballistic single wall carbon nanotube field-effect transistors (CNFETs). For the first time, a universal circuit-compatible CNFET model was implemented with HSPICE. This model includes practical device non-idealities, e.g. the quantum confinement effects in both circumferential and channel length direction, the acoustical/optical phonon scattering in channel region and the resistive source/drain, as well as the real time dynamic response with a transcapacitance array. This model is valid for CNFET for a wide diameter range and various chiralities as long as the carbon nanotube (CNT) is semiconducting.

First Demonstration of AC Gain From a Single-Walled Carbon Nanotube Common-Source Amplifier

First demonstration of AC gain from a single-walled carbon nanotube transistor is presented. A top-gated carbon nanotube field-effect transistor (CNFET) is configured as a common-source amplifier and frequency response function of the amplifier is measured. Evidence of unambiguous signal amplification is observed in time domain as well as frequency domain up to a unity gain frequency of approximately 560 kHz. The observed roll-off in frequency is solely due to the RC time constant of the measurement apparatus. A specifically designed circuit compatible SPICE model for the CNFET is used to model both DC and AC characteristic with the same set of physical parameters for the first time. Good agreement between measurement and simulation is obtained. For a device without the parasitic load capacitance, the predicted intrinsic unity voltage gain frequency is 29 GHz and the cut-off frequency is ~ 50 GHz.

Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections

1D carbon nanotube FET (CNFET)-based circuits offer 4.6times faster FO4 speed and 12times energy-delay product improvement over 32nm node Si CMOS (including diameter and doping variations), provided circuits can be built that are immune to misaligned and metallic nanotubes. A design technique that guarantees correct logic operation in the presence of misaligned nanotubes is also presented.

Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits

Carbon Nanotube Field-Effect Transistors (CNFETs) are promising candidates as extensions to Silicon CMOS due to excellent CV/I device performance. An ideal CNFET inverter fabricated using a perfect CNFET technology can have 5.1 times faster F04 delay and 2.6 times lower energy per cycle compared to a 32nm Silicon CMOS inverter. Two fundamental challenges prevent us from creating CNFET-based logic designs with the advantages quoted above: 1. Misaligned Carbon Nanotubes (CNTs), and 2. Metallic CNTs. Misaligned CNTs can result in incorrect logic function implementations. This paper presents a technique for designing CNFET-based arbitrary logic functions that are guaranteed to be correct even in the presence of a large number of misaligned CNTs.

Designing Circuits with Carbon Nanotubes Open Questions and Some Possible Directions

Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits

Carbon Nanotube Transistor Compact Model

Metrics for Performance Benchmarking of Nanoscale Si and Carbon Nanotube FETs including Device Nonidealities

This paper proposes a simple and accurate expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking. The choice of I_eff=(I_NL + I_NM + I_NH - I_P)/3, where I_NL=I_DS(N-FET) at (V_GS=0.5V_DD, V_DS=V_DD), I_NM=I_DS(N-FET) at (V_GS=0.75V_DD, V_DS=0.75V_DD), I_NH=I_DS(N-FET) at (V_GS=V_DD, V_DS=0.5V_DD), and I_P=I_SD(P-FET) at (V_SG=0.25V_DD, V_SD=0.25V_DD), includes the effects of both the nFET and the pFET of an inverter and accurately captures the inverter delay performance over many CMOS technology nodes and in the presence of device nonidealities. The proposed metric indicates that the performance enhancement of CNFETs over Si MOSFETs is not as large as that predicted by I_Dsat in a circuit environment because of the nonideal I-V characteristics.

Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling (TED)

The theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs) is examined by means of a general ballistic model. A novel approach is used to treat the SBs at the metal-nanotube contacts as mesoscopic scatterers by modifying the distribution functions for carriers in the channel. Noticeable current reduction is observed compared to previous ballistic models without SBs. Evanescent-mode analysis is used to derive a scale length and the potential profile near the contacts for radially symmetric CNFET structures. Band-to-band tunneling current and ambipolar conduction are also treated. The effects of different device geometries and different nanotube chiralities on the drain-current are studied using this simple model. Quantum conductance degradation due to SBs is also observed.

Nanostructured Materials for Interconnects

As integrated circuit's smallest features keep being scaled down according to Moore's Law, the narrowest interconnect wires within state-of-the-art silicon chips have entered the nanoscale regime. Innovative materials engineered at the nanoscale will be required to meet the requirements of future nanoelectronic chips. This article reviews some of the alternative options besides scaled copper for nanoscale local interconnects: conducting polymers, metallized DNA, metallic nanowires and metallic carbon nanotubes. Metallic nanotube is identified as a promising material for future local interconnects.

Modeling Carbon Nanotube Sensors

Carbon nanotube sensors are modeled and their design space analyzed. It is found that semiconducting nanotubes are almost always preferred over metallic nanotubes, intrinsic nanotubes maximize sensor performance, while minimizing static power consumption, and higher biasing points maximize dynamic range, while improving sensitivity. Insights into design of nanoscale sensors for optimal performance are provided, and it is shown that single-molecule analyte detection can be readily achieved with 1 nm diameter nanotubes up to 30um in length.

Carbon Nanotube Transistor Compact Model

The principal challenges for the semiconductor industry at the nanoscale are: (1) power and performance optimization, (2) device fabrication and control of variations at the nanoscale, and (3) integration of a diverse set of materials and devices on the same chip., Nanotechnology has been put forward as the key to meeting many of the challenges of the industry. New physical phenomenon and chemical/biological synthesis techniques are being explored. While there have been significant accomplishments in scientific discovery at the nanoscale, the engineering work that is required to harness the science into manufacturable technologies is just beginning. In this paper, we focus on the use of the carbon nanotube transistor as a logic switch. While very promising experimental results have been published in the past few years, these results are mostly on a single-device level with a focus on scientific discovery. In order to develop a new transistor into a bona fide technology, an engineering approach needs to be adopted. We need to develop the necessary device models and design tools with the appropriate level of abstraction to enable the design of a useful system. This is distinct from the “science” phase of discovery and explanation of physical phenomena. We will describe the development of an HSPICE compact model of the carbon nanotube transistor . The model is physics based and include non-idealities such as carrier scattering and parasitic resistances and parasitic capacitances. Using this model, we perform circuit simulations to assess the effect of material parameter variation of the carbon nanotube on circuit performance. We obtain key information such as the delay variation as a function of the nanotube diameter and the source/drain doping level and thereby establish a realistic assessment of the expected performance of carbon nanotube transistors at the circuit level. This device model is compatible with both digital circuits design (as a logic switch) and analog circuits design (as small signal amplifier). We illustrate the use of this model for small signal analysis through an application example . The development of tools, such as the ones illustrated in this paper, will be necessary for any proposed new device to become a useful technology.

Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance C_gg is decomposed into three major components: 1) capacitance C_gc between the gate and the parallel cylindrical conducting channels (the number of channels >= 1) in dual-layer dielectric materials; 2) outer fringe capacitance C_of between the gate and the source/drain cylinder conductors; and 3) coupling capacitance C_gtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed.

Carbon Nanotube Transistor Circuits – Models and Tools for Design and Performance Optimization

In this paper, we describe the development of device models and tools for the design of new transistors such as the carbon nanotube transistor. An HSPICE model for enhancement mode nanotube transistor has been developed. It can be used for design of nanotube transistor circuits as well as to study performance benefits of the new transistor. A model of the carbon nanotube transistor with Schottky barrier is presented. The model enables device design and performance optimization.

Analysis of the Frequency Response of Carbon Nanotube Transistors

The characterizations of carbon nanotube transistors at high frequencies have so far been hindered by large parasitic and extrinsic capacitances. We present a quantitative analysis of the limitations imposed by probe pad parasitics on single-wall carbon nanotube transistor characterization at gigahertz frequencies. Our analysis reveals the various kinds of frequency responses that can be expected to be measured. Furthermore, we present design guidelines and a suitable device layout to achieve gain and bandwidth at gigahertz frequencies.

Measurability Issues in the Radio-Frequency Characterization of Carbon Nanotubes

We discuss two measurability issues plaguing conventional on-wafer RF measurements with a network analyzer when dealing with quasi 1-D systems, such as carbon nanotubes. Those small-geometry devices typically exhibit an impedance on the order of h/(2e)^2= 12.9 kOhm, resulting in a large intrinsic mismatch with the 50Ohm reference impedance of the network analyzer. We show that the accuracy of the network analyzer is greatly degraded by this mismatch. In addition, the de-embedding of the test fixture is shown to degrade even further the measurement uncertainty. We then propose a potential solution to circumvent these accuracy problems.

Analytical Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass, Carrier Density, and Quantum Capacitance

IEEE IEDM 2007 Technical Digest

An Analytical Derivation of the Density of States, Effective Mass and Carrier Density of Achiral Carbon Nanotubes

An analytical electron density of states (DOS) for zigzag and armchair single-wall carbon nanotubes (CNTs) are derived in this paper. The derivation originates from the tight-binding energy dispersion relation for CNTs and reveals the essential physics such as periodic van-Hove singularities and its dependence on chirality. The DOS derivation is exact and contains no additional approximations or assumptions, except those inherent in the nearest neighbor tight-binding model. In addition, we derive analytical expressions for the group velocity, effective mass, and nondegenerate equilibrium carrier density.

A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors

Due to their excellent electrical properties, metallic carbon nanotubes are promising materials for interconnect wires in future integrated circuits. Simulations have shown that the use of metallic carbon nanotube interconnects could yield more energy efficient and faster integrated circuits. The next step is to build an experimental prototype integrated circuit using carbon nanotube interconnects operating at high speed. Here, we report the fabrication of the first stand-alone integrated circuit combining silicon transistors and individual carbon nanotube interconnect wires on the same chip operating above 1 GHz. In addition to setting a milestone by operating above 1 GHz, this prototype is also a tool to investigate carbon nanotubes on a silicon-based platform at high frequencies, paving the way for future multi-GHz nanoelectronics.