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2009
- Size-dependent phase transitions and morphological control over phase chane properties using colloidal nanoparticle building blocks
  Marissa A. Caldwell, H.S.-Philip Wong, Simone Raoux, Ravisubhash Tangirala, Robert Y. Wang, and Delia J. Milliron, September 9, 2009
- Crystallization times of Ge-Te phase change materials as a function of composition
  Simone Raoux, H.Y. Cheng, Marissa A. Caldwell, H.-S. Philip Wong, August 21, 2009
- Fabrication and Characterization of Emerging Nanoscale Memory
  SangBum Kim, Yuan Zhang, Byoungil Lee, Marissa Caldwell, H.-S. Philip Wong, May 24, 2009
- Fabrication and characterization of emerging nanoscale memory
  SangBum Kim, Yuan Zhang, Byoungil Lee, Marissa Caldwell, and H.-S. Philip Wong, May 24, 2009
- Effect of Parasitic Resistance and Capacitance on Performance of InGaAs HEMT Digital Logic Circuits
  Saeroonter Oh and H.-S. Philip Wong, May 2009
- CMOS technology roadmap projection including parasitic effects
  Lan Wei, Frederic Boeuf, Thomas Skotnicki, H. S. Philip Wong, April 27, 2009
- Effects of carbon source geometry and reactivity on the CVD growth of single-walled carbon nanotubes
  Cara Beasley, Bruce M. Clemens, H-S. Philip Wong, March 25, 2009
- Threshold Voltage and On-Off Ratio Tuning for Multiple-Tube Carbon Nanotube FETs
  Albert Lin, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Lewis Gomez De Arco, Chongwu Zhou, Subhasish Mitra, and H.-S. Philip Wong, January 16, 2009
- Circuit-Level Performance Benchmarking and Scalability Analysis of Carbon Nanotube Transistor Circuits
  Nishant Patil, Jie Deng, Subhasish Mitra, and H.-S. Philip Wong, January 16, 2009
- CMOS-Analogous Wafer-Scale Nanotube-on-Insulator Approach for Submicrometer Devices and Integrated Circuits Using Aligned Nanotubes
  Koungmin Ryu, Alexander Badmaev, Chuan Wang, Albert Lin, Nishant Patil, Lewis Gomez, Akshay Kumar, Subhasish Mitra, H.-S. Philip Wong, and Chongwu Zhou, January 14, 2009
- Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
  L. Wei, J. Deng, L.-W. Chang, K. Kim, C.-T. Chuang and H. -S. P. Wong, January 9, 2009
- Measurement of Subnanosecond Delay Through Multiwall Carbon-Nanotube Local Interconnects in a CMOS Integrated Circuit
  Gael F. Close, Shinichi Yasuda, Bipul Paul, Shinobu Fujita, H.-S. Philip Wong, January 2009

2008
- Physics-Based Compact Model of III-V Heterostructure FETs for Digital Logic Applications
  Saeroonter Oh and H.-S. Philip Wong, December 15, 2008
- Modeling and Performance Comparison of 1-D and 2-D Devices Including Parasitic Gate Capacitance and Screening Effect
  Lan Wei, Jie Deng and H.-S. Philip Wong, November 7, 2008
- Phase Change Nanodots Patterning Using a Self-Assembled Polymer Lithography and Crystallization Analysis
  Y. Zhang, S. Raoux, D. Krebs, L.E. Krupp, T. Topuria, M.A. Caldwell, D.J. Milliron, A. Kellock, P.M. Rice, J.L. Jordan-Sweet, H.-S. P. Wong, October 6, 2008
- Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits
  Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra, October 2008
- Carrier Density and Quantum Capacitance for Semiconducting Carbon Nanotubes
  Jiale Liang, Deji Akinwande, H.-S. Philip Wong, September 29, 2008
- An Analytical Model for Intrinsic Carbon Nanotube FETs
  L. Wei, D. Frank, L. Chang, H.-S. P. Wong, September 15, 2008
- Finite Element Analysis and Analytical Simulations of Suspended Gate-FET for Ultra-low Power Inverters
  Dimitrios Tsamados, Yogesh Singh Chauhan, Christoph Eggimann, Kerem Akarvardar, H.-S. Philip Wong, and Adrian Mihai Ionescu, September 1, 2008
- Integrating Phase-Change Memory Cell with Ge Nanowire Diode for Crosspoint Memory - Experimental Demonstration and Analysis
  SangBum Kim, Yuan Zhang, James P. McVittie, Hemanth Jagannathan, Yoshio Nishi, H.-S. Philip Wong, August 19, 2008
- Fermi-Level Depinning of GaAs for Ohmic Contacts
  Jenny Hu, Donghun Choi, James Harris, Krishna C. Saraswat, and H.-S.Philip Wong, June 23, 2008
- Energy-Reversible Complementary NEM Logic Gates
  Kerem Akarvardar, David Elata, Roger T. Howe, H.-S. Philip Wong, June 23, 2008
- Integrated Wafer-Scale Growth and Transfer of Directional Carbon Nanotubes and Misaligned-Carbon-Nanotube-Immune Logic Structures
  Nishant Patil, Albert Lin, Edward R. Myers, H.-S. Philip Wong, Subhasish Mitra, June 17, 2008
- Effective Drive Current for Sub-45nm Technologies
  Jenny Hu, Jae Eun Park, Greg Freeman, and H.-S.Philip Wong, June 2008
- Hole Mobility Characteristics under Electrical Stress for Surface-Channel Germanium Transistors with High-k Gate Stack
  Jeong-Hyong Yi, Saeroonter Oh, and H.-S. Philip Wong , April 25, 2008
- Extending Technology Roadmap by Selective Device Footprint Scaling and Parasitics Engineering
  Deng, Jie; Wei, Lan; Chang, Li-Wen; Kim, Keunwoo; Chuang, Ching-Te; Wong, H.-S. Philip;, April 23, 2008
- Carbon Nanotube Transistor Compact Model for Circuit Design and Performance Optimization
  Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong, April 1, 2008
- A 1 GHz Integrated Circuit with Carbon Nanotube Interconnects and Silicon Transistors
  Gael F. Close, Shinichi Yasuda, Bipul Paul, Shinobu Fujita, and H.-S. Philip Wong, March 6, 2008
- An Analytical Derivation of the Density of States, Effective Mass and Carrier Density of Achiral Carbon Nanotubes
  Deji Akinwande, Yoshio Nishi, H.-S. Philip Wong, January 1, 2008
- Analytical Modeling of the Suspended-gate FET and Design Insights for Low Power Logic
  K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauhan, G. C. Wan, A. M. Ionescu, R. T. Howe, H.-S. P. Wong, January 1, 2008

2007
- Analytical Model of Carbon Nanotube Electrostatics: Density of States, Effective Mass, Carrier Density, and Quantum Capacitance
  Deji Akinwande, Yoshio Nishi, H.-S. Philip Wong, December 12, 2007
- 1-D and 2-D Devices Performance Comparison Including Parasitic Gate Capacitance and Screening Effect
  Lan Wei, Jie Deng, H.-S. Philip Wong, December 12, 2007
- Design considerations for complementary nanoelectromechanical logic gates
  K. Akarvardar, D. Elata, R. Parsa, G. C. Wan, K. Yoo, J Provine, P. Peumans, R. T. Howe, H.-S.P. Wong, December 10, 2007
- Fabrication and Characterization of Carbon Nanotube Interconnects
  G. F. Close, and H.-S. P. Wong, December 6, 2007
- Synthesis of Metal Chalcogenide Nanodot Arrays Using Block Copolymer-Derived Nanoreactors
  D. Milliron, M. Caldwell and H.-S. P. Wong, September 28, 2007
- Numerical and Analytical Simulations of Suspended Gate FET for Ultra-Low Power Inverters
  D. Tsamados, Y.S. Chauhan, C. Eggimann, K. Akarvardar, H.-S. P. Wong, A.M. Ionescu, September 11, 2007
- Thickness and Stoichiometry Dependence of the Thermal Conductivity of GeSbTe Films
  J. P. Reifenberg, M. A. Panzer, S. Kim, A. M. Gibby, Y. Zhang, S. Wong, H.-S. P. Wong, E. Pop, September 11, 2007
- Modeling and Analysis of Planar-Gate Electrostatic Capacitance of 1-D FET With Multiple Cylindrical Conducting Channels
  Deng, J.; Wong, H.-S. P., September 2007
- Modeling Carbon Nanotube Sensors
  J. Deng, K. Ghosh, H.-S. P. Wong, September 2007
- Emerging Memories
  H.-S. P. Wong, September 2007
- X-Ray Diffraction Studies of Phase Change Nanoparticles Produced by Self-Assembly-based Lithographic Techniques
  S. Raoux, Y. Zhang, D. Milliron, J. Cha, M. Caldwell, C.T. Rettner, J.L. Jordan-Sweet, H.-S. P. Wong, September 2007
- The Synthesis and Characterization of Germanium Chalcogenide Nanoparticles via Single-Source Precursor and Co-precipitation
  M. Caldwell, D. Milliron, H.-S. P. Wong, August 19, 2007
- Analysis of Temperature in Phase Change Memory Scaling
  Kim, S.; Wong, H.-S.P., August 2007
- Carbon Nanotube Transistor Compact Model
  H.-S. P. Wong, July 23, 2007
- Phase Change Nanodot Arrays Fabricated Using a Self-Assembly Diblock Copolymer Approach
  Y. Zhang, H.-S. P. Wong, S. Raoux, J.N. Cha, C.T. Rettner, L.E. Krupp, T. Topuria, D.J. Milliron, P.M. Rice, J.L. Jordan-Sweet, July 2, 2007
- Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic
  K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauan, G. C. Wan, A. M. Ionescu, and H.S.-P. Wong, June 18, 2007
- An Integrated Phase Change Memory Cell With Ge Nanowire Diode For Cross-Point Memory
  Y. Zhang, S. Kim, J.P. McVittie, H. Jagannathan, J.B. Ratchford, C.E.D. Chidsey, Y. Nishi, and H.-S. P. Wong, June 12, 2007
- Automated Design of Misaligned-Carbon-Nanotube-Immune Circuits
  N. Patil, J. Deng, H.-S. P. Wong, and S. Mitra, June 4, 2007
- Phase Transitions and Thermal Properties in GeSbTe (2:2:5)
  J. Reifenberg, S. Kim, Y. Zhang, E. Pop, H.-S. P. Wong, K. Goodson, May 20, 2007
- The Impact of Device Footprint Scaling on High-Performance CMOS Logic Technology
  Deng, J.; Kim, K.; Chuang, C.-T.; Wong, H.-S. P., May 2007
- Transition Behavior of High Density Ordered Phase Change Nanostructure from Diblock Copolymer Template
  Y. Zhang, S. Raoux, J. N. Cha, L. E. Krupp, C. T. Rettner, H.-S. P. Wong, April 10, 2007
- A Composite Circuit Model for NDR Devices in Random Access Memory Cells
  Akinwande, D.; Wong, H.-S.P., April 2007
- Device Footprint Scaling for Ultra Thin Body Fully Depleted SOI
  J. Deng, K. Kim, C.-T. Chuang, H.-S. P. Wong, March 26, 2007
- Design of Imperfection-Immune Carbon Nanotube Field Effect Transistor Circuits
  N. Patil, J. Deng, S. Mitra, H.-S. P. Wong, March 19, 2007
- Schottky-Barrier Carbon Nanotube Field-Effect Transistor Modeling (TED)
  Arash Hazeghi; Tejas Krishnamohan; H.-S. Philip Wong, March 2007
- Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections
  J. Deng, N. Patil, K. Ryu, A. Badmaev, C. Zhou, S. Mitra, H.-S. P. Wong, February 11, 2007
- Biomimetic Approaches for Fabricating High-Density Nanopatterned Arrays
  Jennifer N. Cha, Yuan Zhang, H.-S. Philip Wong, Simone Raoux, Charles Rettner, Leslie Krupp, and Vaughn Deline, January 20, 2007
- Carbon Nanotube Transistor Compact Model
  J. Deng, G.C. Wan and H.-S. Wong, 2007
- Nanostructured Materials for Interconnects
  G.F. Close, H.-S. P. Wong, 2007

2006
- First Demonstration of AC Gain From a Single-Walled Carbon Nanotube Common-Source Amplifier
  I. Amlani. J. Lewis, K. Lee, R. Zhang, J. Deng, H.-S. P. Wong, December 11, 2006
- Theoretical Investigation Of Performance In Uniaxially- and Biaxially-Strained Si, SiGe, and Ge Double-Gate p-MOSFETs
  T. Krishnamohan, C. Jungemann, D. Kim, E. Ungersboeck, S. Selberherr, H.-S. P. Wong, Y. Nishi, and K. Saraswat, December 11, 2006
- Nanotechnology for the Semiconductor Industry
  H.-S. P. Wong, November 12, 2006
- Carbon Nanotube Transistor Circuits – Models and Tools for Design and Performance Optimization
  H.-S. Philip Wong, Jie Deng, Arash Hazeghi, Tejas Krishnamohan, Gordon C. Wan, November 5, 2006
- Analysis of the Frequency Response of Carbon Nanotube Transistors
  D. Akinwande., G.F. Close, and H.-S. P. Wong, September 11, 2006
- High Mobility Materials and Novel Device Structures for High Performance n-MOSFETs
  K. Saraswat and H.-S. P. Wong, September 8, 2006
- A Circuit-Compatible SPICE model for Enhancement Mode Carbon Nanotube Field Effect Transistors
  J. Deng, H.-S. P. Wong, September 6, 2006
- Device Opportunities of Nanotechnology
  H.-S. P. Wong, September 5, 2006
- Measurability Issues in the Radio-Frequency Characterization of Carbon Nanotubes
  G. F. Close and H.-S. P. Wong, June 17, 2006
- Designing Circuits with Carbon Nanotubes Open Questions and Some Possible Directions
  Jie Deng; Patil, N.; Mitra, S.; Wong, H.-S.P., June 17, 2006
- Schottky-Barrier Carbon Nanotube Field Effect Transistor Modeling (IEEE NANO)
  A. Hazeghi, T. Krishnamohan, H.-S. P. Wong, June 17, 2006
- Metrics for Performance Benchmarking of Nanoscale Si and Carbon Nanotube FETs including Device Nonidealities
  Jie Deng; Wong, H.-S.P., June 2006
- Diblock Copolymer Directed Self-Assembly for CMOS Device Fabrication
  L.-W. Chang, H.-S. P. Wong, April 2006
- Device and Technology Challenges for Nanoscale CMOS
  H.-S. P. Wong, March 27, 2006
- Nanoelectronics – Opportunities and Challenges (IJHSES)
  H.-S. P. Wong, March 2006
- Generalized Phase Change Memory Scaling Rule Analysis
  S. Kim, H.-S. P. Wong, February 12, 2006
- Research Opportunities for Nanoscale CMOS
  H.-S. P. Wong, January 30, 2006
- Nanoelectronics - Opportunities and Challenges (IJHSES)
  H.-S. Philip Wong, 2006

2005
- Investigation of Performance limits of III-V Double-Gate n-MOSFETs
  A. Pethe, T. Krishnamohan, D. Kim, S. Oh, H.-S. P. Wong, Y. Nishi, and K. C. Saraswat, December 5, 2005
- Circuit Analysis of Sublithographic Nanodevice Logic Array
  J. Deng, H.-S. P. Wong, November 4, 2005
- Metric of Performance Benchmarking of Nanoscale Si and Carbon Nanotube FET
  J. Deng, H.-S. P. Wong, November 2, 2005
- Deterministic Nanowire Growth
  J. Woodruff, J. Ratchford, H. Jagannathan, H. Adhikari, H.-S.P. Wong, C.E.D. Chidsey, October 2005
- Nanoelectronics: Nanotubes, Nanowires, Molecules, and Novel Concepts
  H.-S. P. Wong, September 12, 2005
- Advanced CMOS Devices – A Tutorial From Practical Options to Innovative Concepts: Part I – Conventional Devices and Technology Options
  H.-S. P. Wong, May 15, 2005
- Advanced CMOS Devices – A Tutorial From Practical Options to Innovative Concepts: Part II – Exploratory Devices and Approaches
  H.-S. P. Wong, May 15, 2005
- Nanoelectronics: Opportunities and Challenges (AVS)
  H.-S. P. Wong, March 21, 2005
- Beyond the Conventional Transistor
  H.-S. P. Wong, March 16, 2005
- Nanotechnology Overview
  H.-S. P. Wong, March 15, 2005
- The End of CMOS Scaling: Toward the Introduction of New Materials and Structural Changes to Improve MOSFET Performance
  T. Skotnicki, J. A. Hutchby, T.-J. King, H.-S. P. Wong, F. Beouff, January 31, 2005

2004
- Nanoelectronics: Opportunities and Challenges (WOFE)
  H.-S. P. Wong, December 18, 2004
- Nanodevices Beyond Silicon: Device and Circuit Implications
  H.-S. Philip Wong, October 18, 2004