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2017
R. Yang, Li, H., Smithe, K. K. H., Kim, T. R., Okabe, K., Pop, E., Fan, J. A., and Wong, H. - S. Philip, “2D molybdenum disulfide (MoS 2) transistors driving RRAMs with 1T1R configuration”, in Electron Devices Meeting (IEDM), 2017 IEEE International, 2017.
W. Hwang, Aly, M. M. Sabry, Malviya, Y. H., Gao, M., Wu, T. F., Kozyrakis, C., Wong, H. - S. Philip, and Mitra, S., “3D nanosystems enable embedded abundant-data computing: special session paper”, in Proceedings of the Twelfth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis Companion, 2017.
J. - C. Liu, Magyari-Kope, B., Qin, S., Zheng, X., Philip Wong, H. - S., and Hou, T. - H., “AC stress and electronic effects on SET switching of HfO2 RRAM”, Applied Physics Letters, vol. 111, p. 093502, 2017.
M. Marcel Shulaker, Wei, H., Mitra, S., and Wong, H. - S. Philip, “Carbon Nanotubes for Monolithic 3D ICs”, in Carbon Nanotubes for Interconnects, Springer, 2017, pp. 315–333.
C. - C. Chang, Liu, J. - C., Shen, Y. - L., Chou, T., Chen, P. - C., Wang, I. - T., Su, C. - C., Wu, M. - H., Hudec, B., Chang, C. - C., and others, “Challenges and opportunities toward online training acceleration using RRAM-based hardware neural network”, in Electron Devices Meeting (IEDM), 2017 IEEE International, 2017.
Y. Shi, Pan, C., Chen, V., Raghavan, N., Pey, K. L., Puglisi, F. M., Pop, E., Wong, H. - S. P., and Lanza, M., “Coexistence of volatile and non-volatile resistive switching in 2D h-BN based electronic synapses”, in Electron Devices Meeting (IEDM), 2017 IEEE International, 2017.
D. Guo, Tung, M., Karageorgos, I., Wong, H. - S. Philip, and Wong, M. D. F., “Density driven placement of sub-DSA resolution assistant features (SDRAFs)”, in Design-Process-Technology Co-optimization for Manufacturability XI, 2017.
H. Li, Huang, P., Gao, B., Liu, X., Kang, J., and Wong, H. - S. Philip, “Device and Circuit Interaction Analysis of Stochastic Behaviors in Cross-Point RRAM Arrays”, IEEE Transactions on Electron Devices, vol. 64, pp. 4928–4936, 2017.
H. Li, Wu, T. F., Mitra, S., and Wong, H. - S. Philip, “Device-architecture co-design for hyperdimensional computing with 3d vertical resistive switching random access memory (3D VRRAM)”, in VLSI Technology, Systems and Application (VLSI-TSA), 2017 International Symposium on, 2017.
S. W. Fong, Neumann, C. M., Yalon, E., Rojo, M. Muñoz, Pop, E., and Wong, H. - S. Philip, “Dual-Layer Dielectric Stack for Thermally Isolated Low-Energy Phase-Change Memory”, IEEE Transactions on Electron Devices, vol. 64, pp. 4496–4502, 2017.
S. W. Fong, Neumann, C. M., and Wong, H. - S. Philip, “Dual-layer dielectric stack for thermally-isolated low-power phase-change memory”, in Memory Workshop (IMW), 2017 IEEE International, 2017.
T. N. Theis and Wong, H. - S. Philip, “The end of Moore's Law: A new beginning for information technology”, Computing in Science & Engineering, vol. 19, pp. 41–50, 2017.
P. Yao, Wu, H., Gao, B., Eryilmaz, S. Burc, Huang, X., Zhang, W., Zhang, Q., Deng, N., Shi, L., Wong, H. - S. Philip, and others, “Face classification using electronic synapses”, Nature communications, vol. 8, p. 15199, 2017.
S. Datta, Seabaugh, A., Niemier, M., Raychowdhury, A., Schlom, D., Jena, D., Xing, G., Wong, H. - S. Philip, Pop, E., Salahuddin, S., and others, “In quest of the next information processing substrate”, in Design Automation Conference (DAC), 2017 54th ACM/EDAC/IEEE, 2017.
Y. Feng, Zhang, K., Li, H., Wang, F., Zhou, B., Fang, M., Wang, W., Wei, J., and Wong, H. S. Philip, “In situ visualization and detection of surface potential variation of mono and multilayer MoS2 under different humidities using Kelvin probe force microscopy”, Nanotechnology, vol. 28, p. 295705, 2017.
Z. Zhang, Yuan, F., Liu, C., Zhou, F., Yau, H. Man, Lu, W., Qiu, X. Y., Wong, H. - S. Philip, Chai, Y., and Dai, J., “In-situ Observation of Cu Filaments Evolution in SiO 2 layer”, Microscopy and Microanalysis, vol. 23, pp. 1622–1623, 2017.
K. B. Parizi, Xu, X., Pal, A., Hu, X., and Wong, H. S. Philip, “ISFET pH sensitivity: Counter-Ions play a key role”, Scientific reports, vol. 7, p. 41305, 2017.
X. Hu, Aggarwal, K., Yang, M. X., Parizi, K. B., Xu, X., Akin, D., Poon, A. S. Y., and Wong, H. - S. Philip, “Micrometer-Scale Magnetic-Resonance-Coupled Radio-Frequency Identification and Transceivers for Wireless Sensors in Cells”, Physical Review Applied, vol. 8, p. 014031, 2017.
S. W. Fong, Neumann, C. M., and Wong, H. - S. Philip, “Phase-Change Memory—Towards a Storage-Class Memory”, IEEE Transactions on Electron Devices, vol. 64, pp. 4374–4385, 2017.
M. X. Yang, Dowling, K., Senesky, D., and Wong, H. - S. Philip, “Rapid Prototyping Tape Stencils for the Application of Solder Paste”, in International Symposium on Microelectronics, 2017.
F. Yuan, Zhang, Z., Liu, C., Zhou, F., Yau, H. Man, Lu, W., Qiu, X., Wong, H. - S. Philip, Dai, J., and Chai, Y., “Real-time observation of the electrode-size-dependent evolution dynamics of the conducting filaments in a SiO2 layer”, ACS nano, vol. 11, pp. 4097–4104, 2017.
H. Li, Wu, T. F., Mitra, S., and Wong, H. - S. Philip, “Resistive RAM-centric computing: Design and modeling methodology”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, pp. 2263–2273, 2017.
H. - Y. Chen, Brivio, S., Chang, C. - C., Frascaroli, J., Hou, T. - H., Hudec, B., Liu, M., Lv, H., Molas, G., Sohn, J., and others, “Resistive random access memory (RRAM) technology: From material, device, selector, 3D integration to bottom-up fabrication”, Journal of Electroceramics, vol. 39, pp. 21–38, 2017.
M. X. Yang, Wang, B., Hu, X., and Wong, H. - S. Philip, “A simple technique to design microfluidic devices for system integration”, Analytical Methods, vol. 9, pp. 6349–6356, 2017.
C. - W. Hsu, Zheng, X., Wu, Y., Hou, T. - H., and Wong, H. - S. Philip, “Statistical study of RRAM MLC SET variability induced by filament morphology”, in Reliability Physics Symposium (IRPS), 2017 IEEE International, 2017.

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