CMOS Technology Scaling Trend
This section below is no longer updated. This data set (link below) is a compilation of the historical CMOS technology scaling data presented in ITRS, journals, and conferences including IEDM and VLSI Technology from 1988 and onward. Chi-Shuen Lee, Jieying Luo, and H.-S. Philip Wong at Stanford University compiled the data; Thomas N. Theis at Columbia University provided the data origninally compiled by Robert W. Keyes at IBM T.J. Watson Research Center and published in Figure 1 of Rolf Landauer's 1988 paper.
The historical scaling trend of logic switching energy and integration density were published in Figure 1 and 2, respectively in .
 Thomas N. Theis, H.-S. Philip Wong, "The End of Moore’s Law: A New Beginning for Information Technology," Computing in Science and Engineering, IEEE CS and AIP, March/April, 2017
cmos_scaling_trend_v5.zip (most updated version on the nano.stanford.edu site)
Link 2 (permanent link at the Stanford Data Repository)
note on usage
If you use the data in a publication or a presentation, please cite this work:
H.-S. P. Wong, C.-S. Lee, J. Luo, C.-H. Wang, “CMOS Technology Scaling Trend,” https://nano.stanford.edu/cmos-technology-scaling-trend, accessed May 12, 2022.
contacts for inquiries
Chi-Shuen Lee - chishuen [at] stanford [dot] edu
H.-S. Philip Wong - hspwong [at] stanford [dot] edu