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Device-to-System Performance Evaluation Tool

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Device-to-System Performance EvaLuation tool (DISPEL)

The Stanford Device-to-System Performance EvaLuation tool (DISPEL) is a platform that integrates transistor/interconnect technology modeling, parasitic extraction, standard cell library characterization, logic synthesis, cell placement and routing, and timing analysis to evaluate system-level performance of new transistor and interconnect technologies. DISPEL aims to bridge CMOS technology developers and circuit/system designers to arrive at a complete picture for evaluating options for future device technologies.


A link will be provided as soon as the package is available for download.


Chi-Shuen (Vince) Lee - chishuen [at] stanford [dot] edu

Related Publications

C.-S. Lee, B. Cline, S. Sinha, G. Yeric, and H.-S. P. Wong, “32-bit Processor Core at 5-nm Technology: Analysis of Transistor and Interconnect Impact on VLSI System Performance,” in Proc. IEEE Int. Electron Devices Meeting (IEDM), pp. 28.3.1–28.3.4, Dec. 2016.

content snippets

Flowchart of PDK Development and Physical Design