Stanford RRAM Model

Stanford-PKU RRAM Model

The Stanford-PKU RRAM Model is a SPICE-compatible compact model which describes switching performance for bipolar metal oxide RRAM. In principle, this model has no limitations on the size of the RRAM cell. The complex process of ion and vacancy migration was simplified into the growth of a single dominant filament that preserved the essential switching physics. The size of the tunneling gap (g), which is the distance between the tip of the filament and the opposite electrode, is the primary variable determining device resistance. The current conduction is exponentially dependent on the tunneling gap distance. This distance is found by calculating the growth of the gap, taking into consideration the electric field, temperature-enhanced oxygen ion migration, and local temperature due to Joule heating. In addition, stochastic and temperature-dependent filament movement (δg) is also included. The RRAM model can be instantiated directly in HSPICE netlists to explore the impacts of RRAM on the circuit performance. It is an accurate and handy tool for design exploration and verification of RRAM circuits.

Note: HSPICE H-2013.03-SP2 is the recommended software.

Downloads

Stanford RRAM Model v1.0.0

We recommend users to download the supported version v1.0.0 of the model from the NSF hanoHUB NEEDS website.

Download the Verilog-A RRAM model v1.0.0. Please cite [1] if you use the model/data in your work.

Stanford-PKU RRAM Model v2.0.0 beta

This version v2.0.0 beta distributed on Stanford Nano Group website is a beta version for our own collaborators and advanced users. Please contact RRAM Model Developer Mailing List (nano_rram_model [at] list [dot] stanford [dot] edu) to request access and discuss your use of the model with the developers at Peking University and Stanford University.

Download the Verilog-A RRAM model v2.0.0 beta. Please cite [2] if you use the model/data in your work.

Contact

RRAM Model Developer Mailing List
rram-compact-model-developer [at] list [dot] stanford [dot] edu
Current Developers
Zizhen (Jane) Jiang - jiangzz [at] stanford [dot] edu
Shengjun (Sophia) Qin - sjqin [at] stanford [dot] edu
Haitong Li - haitongl [at] stanford [dot] edu

Contributors

Zizhen Jiang, Haitong Li, Jesse H. Engel, Shimeng Yu, Ximeng Guan

Related Publications

[1] Zizhen Jiang, Yi Wu, Shimeng Yu, Lin Yang, Kay Song, Zia Karim, and H. -S. Philip Wong, "A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification," IEEE Transactions on Electron Devices, vol. 63, no. 5, pp. 1884-1892, May 2016. doi: 10.1109/TED.2016.2545412

[2] Haitong Li, Zizhen Jiang, Peng Huang, Yi Wu, Hong-Yu Chen, Bin Gao, Xiaoyan Liu, Jinfeng Kang, and H.-S. Philip Wong, "Variation-aware, reliability-emphasized design and optimization of RRAM using SPICE model," Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE '15). EDA Consortium, San Jose, CA, USA, 1425-1430.

[3] Zizhen Jiang, Shimeng Yu, Yi Wu, Jesse H. Engel, Ximeng Guan, and H. –S Philip Wong, “Verilog-A Compact Model for Oxide-based Resistive Random Access Memory,” Simulation of Semiconductor Processes and Devices (SISPAD), 2014 International Conference on, vol., no., pp.41,44, 9-11 Sept. 2014 doi: 10.1109/SISPAD.2014.6931558

[4] Shimeng Yu, Bin Gao, Zheng Fang, Hongyu Yu, Jinfeng Kang, and H.-S. Philip Wong, "A neuromorphic visual system using RRAM synaptic devices with Sub-pJ energy and tolerance to variability: Experimental characterization and large-scale modeling," Electron Devices Meeting (IEDM), 2012 IEEE International , vol., no., pp.10.4.1,10.4.4, 10-13 Dec. 2012, doi: 10.1109/IEDM.2012.6479018

[5] Ximeng Guan, Shimeng Yu, and H.-S. Philip Wong, "A SPICE Compact Model of Metal Oxide Resistive Switching Memory With Variations," Electron Device Letters, IEEE , vol.33, no.10, pp.1405,1407, Oct. 2012, doi: 10.1109/LED.2012.2210856