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Technology Integration Trend

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Section - Technology Integration Trend

outline

This data set (link below) is a compilation of the historical technology integration data including NAND Flash, DRAM, SRAM presented in ITRS, journals, and conferences including IEDM , VLSI Technology and ISSCC from 1988 and onward. This data set also contains CPU, GPU data from Intel, NVIDIA and AMD. W.-C. Chen, Haitong Li, Shengjun Qin, C.-H. Wang and H.-S. Philip Wong at Stanford University, Kerem Akarvardar at TSMC and Mohamed M. Sabry at Nanyang Technological University compiled the data;

Figure 1. shows the correlation between transistor count and DRAM capacity. Figure 2. shows the NAND Flash density trend over years. Figure 3. shows the correlation between the number of cores in GPU and its DRAM capacity over years.

Download:

technology_integration_trend_v10.zip (most updated version on the nano.stanford.edu site)

Permanent Link (permanent link at the Stanford Data Repository)

 

note on usage

If you use the data in a publication or a presentation, please cite this work:

H.-S. P. Wong, Kerem Akarvardar, W.-C. Chen, Haitong Li, Shengjun Qin, Mohamed M. Sabry, C.-H. Wang, “Technology Integration Trend,” accessed May 19, 2022.

contacts for inquiries

Wei-Chen Chen - weichen9 [at] stanford [dot] edu

H.-S. Philip Wong - hspwong [at] stanford [dot] edu

content snippets

DRAM Transistor Correlation
NAND 2D 3D
GPU Compute Memory Capacity