Logic devices beyond the silicon CMOS device scaling roadmap. Project scope covers new device concepts, device physics, circuit design, modeling, and device fabrication using novel nanoelectronic materials such as carbon nanotube and graphene as well as novel concepts such as nanoelectromechanical (NEM) relays.
We work on circuit-level performance modeling and optimization for end-of-the-roadmap CMOS devices. As devices scale to small dimensions, parasitic capacitances and parasitic resistances play an increasingly important role in circuit/system level performance. We have developed accurate parasitic capacitance and parasitic resistance models to enable circuit/device optimization and to explore new device design options. Compact models for emerging devices such as III-V FETs, carbon nanotube transistor have been developed and continually being refined to enable performance benchmarking and technology assessment at the device and circuit level.
We continue to develop and enhance our carbon nanotube transistor compact device model for circuit simulation. System-level optimization is enabled by the development of non-iterative compact models of carbon nanotube transistors. We are working on robust circuit design and fabrication for carbon nanotube and graphene electronics including active devices (carbon nanotubes) and interconnects (graphene). We develop synthesis techniques to achieve high-density, aligned growth of carbon nanotubes as well as low temperature carbon nanotube growth for electronics applications. Both digital logic and high-frequency analog applications are explored.
Nanoelectromechanical (NEM) relay represents a departure from the conventional transistors and memories and offers unique advantages such as zero off-state leakage and energy-reversible operation for low standby power and low dynamic power. We work on experimental fabrication of NEM relay and circuits as well as the development of modeling tools for device design and circuit design.
Last modified Thu, 24 Jan, 2013 at 15:36