Complementary Gain Cell and Interface Engineering

Oxide semiconductor FETs leverage wide-bandgap channel materials such as Indium Tungsten Oxide (IWO) to achieve exceptionally low leakage currents, enabling reliable operation at relatively low supply voltages and strong data retention for memories like gaincells. Their compatibility with back-end-of-line process temperatures also supports seamless integration into advanced memory and logic systems.

This project focuses on integrating n- and p-type oxide semiconductor technologies for complementary gaincells and utilizing interface engineering strategies. Through these approaches, we aim to systematically understand and enhance key performance factors such as threshold voltage control, reduced capacitive coupling, and improved gain cell retention.