RRAM-CMOS Compute-In-Memory chip presented at ISSCC 2020:

W. Wan, R. Kubendran, S. B. Eryilmaz, W. Zhang, Y. Liao, D. Wu, S. Deiss, B Gao, P. Raina, S. Joshi, H. Wu, G. Cauwenberghs, and H.-S. P. Wong, "A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models‬," International Solid-State Circuits Conference (ISSCC), Feb. 2020

Demo presented at the ISSCC demo session: https://youtu.be/VWgVv50Yt84

Last modified Sun, 12 Apr, 2020 at 20:45