Stanford University III-V Compact Model

This is a physics-based Compact Model of III-V Field-Effect Transistors (FETs) for Logic Applications.The model was designed for n-type transistors consisted of III-V materials. The default material parameters are for the InGaAs/AlInAs material system. Other III-V materials can be implemented by adjusting the material parameters. Limitations to device dimensions mostly originate from the 2D short channel effects model. However, certain unphysical combinations of the parameters may give unphysical results.The model has been verified through comparison with multiple experimental results.


Click HERE to download the Stanford III-V model


Saeroonter Oh - sroonter [at] gmail [dot] com


Saeroonter Oh


S. Oh and H.-S. P. Wong, A Physics-Based Compact Model of III-V FETs for Digital Logic Applications: Current-Voltage and Capacitance-Voltage Characteristics, IEEE Trans. Electron Devices, vol. 56, no. 12, pp. 2917 - 2924, 2009

S. Oh, H.-S. P. Wong, Physics-based Compact Model for III-V Digital Logic FETs Including Gate Tunneling Leakage and Parasitic Capacitance, IEEE Trans. Electron Devices, Vol. 58, No. 4, pp. 1068 - 1075, 2011.

Last modified Wed, 27 Nov, 2019 at 14:26