Our work on RRAM-based Compute-In-Memory chip was presented at the 2020 Symposia on VLSI Technology & Circuits (Paper TM2.2 & Demo Session). The chip uses RRAM crossbar array to perform in-memory matrix-vector multiplication to accelerate neural network inference. The computation is simultaneously energy-efficient and accurate thanks to a novel voltage-mode sensing scheme that we designed.
We first presented the chip at the 2020 ISSCC conference (paper 33.1), where we focused on the architecture reconfigurability. At the 2020 VLSI conference, we discussed the sensing and weight mapping schemes in details.
Here is a link for chip demo video: https://youtu.be/b7ITxmfaLBk .
Here are the papers describing the chip:
W. Wan, R. Kubendran, B. Gao, S. Joshi, P. Raina, H. Wu, G. Cauwenberghs, H.-S. P. Wong, “A Voltage-Mode Sensing Scheme with Differential-Row Weight Mapping For Energy-Efficient RRAM-Based In-Memory Computing,” Symp. VLSI Technology, June 15 – 19, 2020.
W. Wan, R. Kubendran, S. B. Eryilmaz, W. Zhang, Y. Liao, D. Wu, S. Deiss, B Gao, P. Raina, S. Joshi, H. Wu, G. Cauwenberghs, and H.-S. P. Wong, "A 74 TMACS/W CMOS-RRAM Neurosynaptic Core with Dynamically Reconfigurable Dataflow and In-situ Transposable Weights for Probabilistic Graphical Models," International Solid-State Circuits Conference (ISSCC), Feb. 2020.
Last modified Tue, 15 Dec, 2020 at 21:35